Preliminary Datasheet P9415 (IDT) - 10
| 制造商 | IDT |
| 描述 | Medium Power Wireless Transmitter/Receiver (TRx) |
| 页数 / 页 | 26 / 10 — Theory of Operation / Application/ Descriptive Content Figure 3. Internal … |
| 修订版 | 20190829 |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
Theory of Operation / Application/ Descriptive Content Figure 3. Internal Block Diagram
该数据表的模型线
文件文字版本
P9415 Preliminary Datasheet
Theory of Operation / Application/ Descriptive Content Figure 3. Internal Block Diagram
BST1 BST2 nEN LDO5P0 VRECT nEN&UVLO LDO5V AC1 BIAS M_LDO AC2 VOUT T/RX control 500MHz OSC Is_out G P Is_ VOUT IO tx LDO1P8 LDO1P8 VRECT ECLAMP Gate ECLAMP_DRV AC1 AC2 Driver DAC Freq Det 12b ADC +Comp CMA1 CMA2 CMB1 CMB2 ARM M0 Controller (w/ 24KB MTP, 8 KB RAM) V Is V R _ R E o E C u F T t AFE(TX) OSC - OVP + PCLAMP 60MHz l Load Digital IO (GPIO) DEMOD OD0(SCL)/OD1(SDA)/GP0-GP6/OD2-OD4 © 2019 IDT A Renesas Company. 10 Revision 0.8 August 29, 2019
Theory of Operation / Application/ Descriptive Content Figure 3. Internal Block Diagram
BST1 BST2 nEN LDO5P0 VRECT nEN&UVLO LDO5V AC1 BIAS M_LDO AC2 VOUT T/RX control 500MHz OSC Is_out G P Is_ VOUT IO tx LDO1P8 LDO1P8 VRECT ECLAMP Gate ECLAMP_DRV AC1 AC2 Driver DAC Freq Det 12b ADC +Comp CMA1 CMA2 CMB1 CMB2 ARM M0 Controller (w/ 24KB MTP, 8 KB RAM) V Is V R _ R E o E C u F T t AFE(TX) OSC - OVP + PCLAMP 60MHz l Load Digital IO (GPIO) DEMOD OD0(SCL)/OD1(SDA)/GP0-GP6/OD2-OD4 © 2019 IDT A Renesas Company. 10 Revision 0.8 August 29, 2019