Datasheet TMD2635 (AustriaMicroSystems) - 9

TMD2635 −
Detailed Description
Detailed Description Proximity Operation
By varying gain, VCSEL drive current, number of VCSEL pulses and VCSEL pulse duration the proximity detection range can be adjusted.
Proximity
Proximity results are affected by three fundamental factors: the integrated IR VCSEL emission, IR reception, and environmental factors, including target distance and surface reflectivity. The IR reception signal path begins with IR detection from a photodiode and ends with the 14-bit proximity result in PDATA register. Signal from the photodiode is amplified, and offset adjusted to optimize performance. Offset correction or cross-talk compensation is accomplished by adjustment to the POFFSET register. The analog circuitry of the device applies the offset value as a subtraction to the signal accumulation; therefore a positive offset value has the effect of decreasing the results.
I²C Characteristics
The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and fast clock frequency modes with a chip address of 0x39. Read and write transactions comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive read transactions, the future/repeated I²C read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address + 1.
Alternate I²C Address Option
If the SDA and SCL pins are swapped as shown below, the device will switch to an alternate I²C address. This allows two devices to reside on the same bus. After power is applied to the devices, a single dummy I²C access (read or write with valid I²C stop) to any address or device on the same bus is required to initialize the devices to their respective I²C addresses. The devices will generate an NOT-ACKNOWLEDGE (NACK) during this initial dummy access.
ams Datasheet Page 9
[v1-00] 2019-Jul-17 Document Feedback Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignment Absolute Maximum Ratings Electrical Characteristics Timing Characteristics Detailed Description Proximity Operation Proximity I²C Characteristics Alternate I²C Address Option I²C Write Transaction I²C Read Transaction Simplified State Diagram Register Description ENABLE Register (0x80) PRATE Register (0x82) PILTL Register (0x88) PILTH Register (0x89) PIHTL Register (0x8A) PIHTH Register (0x8B) PERS Register (0x8C) CFG0 Register (0x8D) PCFG0 Register (0x8E) PCFG1 Register (0x8F) REVID Register (0x91) ID Register (0x92) STATUS Register (0x9B) PDATAL Register (0x9C) PDATAH Register (0x9D) REVID2 Register (0xA6) SOFTRST Register (0xA8) PWTIME Register (0xA9) CFG8 Register (0xAA) CFG3 Register (0xAB) CFG6 Register (0xAE) PFILTER Register (0xB3) POFFSETL Register (0xC0) POFFSETH Register (0xC1) CALIB Register (0xD7) CALIBCFG Register (0xD9) CALIBSTAT Register (0xDC) INTENAB Register (0xDD) FAC_L Register (0xE5) FAC_H Register (0xE6) TEST9 Register (0xF9) Application Information PCB Pad Layout Packaging Drawings Tape & Reel Information Soldering & Storage Information Storage Information Moisture Sensitivity Shelf Life Floor Life Rebaking Instructions Laser Eye Safety Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide