Datasheet MCP6V16, MCP6V16U, MCP6V17, MCP6V19 (Microchip) - 6
| 制造商 | Microchip |
| 描述 | 7.5 μA, 80 kHz Zero-Drift Op Amps |
| 页数 / 页 | 52 / 6 — MCP6V16/6U/7/9. 1.3. Timing Diagrams. 1.4. Test Circuits. FIGURE 1-1:. … |
| 文件格式/大小 | PDF / 3.8 Mb |
| 文件语言 | 英语 |
MCP6V16/6U/7/9. 1.3. Timing Diagrams. 1.4. Test Circuits. FIGURE 1-1:. MCP6V1X. FIGURE 1-4:. FIGURE 1-2:. FIGURE 1-5:. FIGURE 1-3:
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MCP6V16/6U/7/9 1.3 Timing Diagrams 1.4 Test Circuits
The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors 1.6V to 5.5V V 1.6V 0V out as discussed in Section 4.3.10, Supply Bypassing DD and Filtering. RN is equal to the parallel combination of tSTR 1.001(V R DD/3) F and RG to minimize bias current effects. VOUT 0.999(VDD/3) VDD 1 µF R
FIGURE 1-1:
Amplifier Start Up. V N IN RISO VOUT
MCP6V1X
VIN CL RL 100 nF V t DD/3 STL VOS + 100 µV V R L V G RF OS VOS – 100 µV
FIGURE 1-4:
AC and DC Test Circuit for Most Noninverting Gain Conditions.
FIGURE 1-2:
Offset Correction Settling Time. VDD 1 µF R V V N DD/3 IN RISO VOUT
MCP6V1X
tODR CL RL 100 nF VIN VDD V t R L ODR G RF VOUT VDD/2
FIGURE 1-5:
AC and DC Test Circuit for Most Inverting Gain Conditions. VSS The circuit in Figure 1-6 tests the input’s dynamic
FIGURE 1-3:
Output Overdrive Recovery. behavior (i.e., IMD, tSTR, tSTL and tODR). The potentiometer balances the resistor network (VOUT should equal VREF at DC). The op amp’s Common- mode input voltage is VCM = VIN/2. The error at the input (VERR) appears at VOUT with a noise gain of 10 V/V. 11.0 kΩ 100 kΩ 500Ω 0.1% 0.1% 25 turn VREF = VDD/3 VDD RISO 1 µF 0Ω VOUT VIN 100 nF CL RL
MCP6V1X
20 pF open VL 11.0 kΩ 100 kΩ 249Ω 0.1% 0.1% 1%
FIGURE 1-6:
Test Circuit for Dynamic Input Behavior. DS20006204A-page 6 2019 Microchip Technology Inc. Document Outline 7.5 µA, 80 kHz Zero-Drift Op Amps Features Typical Applications Design Aids Related Parts Description Package Types Typical Application Circuit 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Common-Mode Voltage with VDD = 1.6V. FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-11: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C. FIGURE 2-12: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C. FIGURE 2-13: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-14: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-15: Input Common-Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-16: Output Voltage Headroom vs. Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Power-on Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-21: CMRR and PSRR vs. Frequency. FIGURE 2-22: Open-Loop Gain vs. Frequency with VDD = 1.6V. FIGURE 2-23: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-27: Closed-Loop Output Impedance vs. Frequency with VDD = 1.6V. FIGURE 2-28: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-29: Channel-to-Channel Separation vs. Frequency. FIGURE 2-30: Maximum Output Voltage Swing vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-31: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-32: Input Noise Voltage Density vs. Input Common-Mode Voltage. FIGURE 2-33: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-34: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-35: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.6V. FIGURE 2-36: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V. 2.5 Time Response FIGURE 2-37: Input Offset Voltage vs. Time at Power Up. FIGURE 2-38: The MCP6V16/6U/7/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-39: Noninverting Small Signal Step Response. FIGURE 2-40: Noninverting Large Signal Step Response. FIGURE 2-41: Inverting Small Signal Step Response. FIGURE 2-42: Inverting Large Signal Step Response. FIGURE 2-43: Slew Rate vs. Ambient Temperature. FIGURE 2-44: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-45: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.3 Application Tips FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO Values for Capacitive Loads. FIGURE 4-9: Output Load. FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.4 Typical Applications FIGURE 4-11: Simple Design. FIGURE 4-12: RTD Sensor. FIGURE 4-13: Offset Correction. FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 Microchip Advanced Part Selector (MAPS) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: REVISION HISTORY Revision A (July 2019) Product Identification System Trademarks Worldwide Sales and Service
MCP6V16/6U/7/9 1.3 Timing Diagrams 1.4 Test Circuits
The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors 1.6V to 5.5V V 1.6V 0V out as discussed in Section 4.3.10, Supply Bypassing DD and Filtering. RN is equal to the parallel combination of tSTR 1.001(V R DD/3) F and RG to minimize bias current effects. VOUT 0.999(VDD/3) VDD 1 µF R
FIGURE 1-1:
Amplifier Start Up. V N IN RISO VOUT
MCP6V1X
VIN CL RL 100 nF V t DD/3 STL VOS + 100 µV V R L V G RF OS VOS – 100 µV
FIGURE 1-4:
AC and DC Test Circuit for Most Noninverting Gain Conditions.
FIGURE 1-2:
Offset Correction Settling Time. VDD 1 µF R V V N DD/3 IN RISO VOUT
MCP6V1X
tODR CL RL 100 nF VIN VDD V t R L ODR G RF VOUT VDD/2
FIGURE 1-5:
AC and DC Test Circuit for Most Inverting Gain Conditions. VSS The circuit in Figure 1-6 tests the input’s dynamic
FIGURE 1-3:
Output Overdrive Recovery. behavior (i.e., IMD, tSTR, tSTL and tODR). The potentiometer balances the resistor network (VOUT should equal VREF at DC). The op amp’s Common- mode input voltage is VCM = VIN/2. The error at the input (VERR) appears at VOUT with a noise gain of 10 V/V. 11.0 kΩ 100 kΩ 500Ω 0.1% 0.1% 25 turn VREF = VDD/3 VDD RISO 1 µF 0Ω VOUT VIN 100 nF CL RL
MCP6V1X
20 pF open VL 11.0 kΩ 100 kΩ 249Ω 0.1% 0.1% 1%
FIGURE 1-6:
Test Circuit for Dynamic Input Behavior. DS20006204A-page 6 2019 Microchip Technology Inc. Document Outline 7.5 µA, 80 kHz Zero-Drift Op Amps Features Typical Applications Design Aids Related Parts Description Package Types Typical Application Circuit 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Common-Mode Voltage with VDD = 1.6V. FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-11: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C. FIGURE 2-12: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C. FIGURE 2-13: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-14: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-15: Input Common-Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-16: Output Voltage Headroom vs. Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Power-on Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-21: CMRR and PSRR vs. Frequency. FIGURE 2-22: Open-Loop Gain vs. Frequency with VDD = 1.6V. FIGURE 2-23: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-27: Closed-Loop Output Impedance vs. Frequency with VDD = 1.6V. FIGURE 2-28: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-29: Channel-to-Channel Separation vs. Frequency. FIGURE 2-30: Maximum Output Voltage Swing vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-31: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-32: Input Noise Voltage Density vs. Input Common-Mode Voltage. FIGURE 2-33: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-34: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-35: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.6V. FIGURE 2-36: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V. 2.5 Time Response FIGURE 2-37: Input Offset Voltage vs. Time at Power Up. FIGURE 2-38: The MCP6V16/6U/7/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-39: Noninverting Small Signal Step Response. FIGURE 2-40: Noninverting Large Signal Step Response. FIGURE 2-41: Inverting Small Signal Step Response. FIGURE 2-42: Inverting Large Signal Step Response. FIGURE 2-43: Slew Rate vs. Ambient Temperature. FIGURE 2-44: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-45: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.3 Application Tips FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO Values for Capacitive Loads. FIGURE 4-9: Output Load. FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.4 Typical Applications FIGURE 4-11: Simple Design. FIGURE 4-12: RTD Sensor. FIGURE 4-13: Offset Correction. FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 Microchip Advanced Part Selector (MAPS) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: REVISION HISTORY Revision A (July 2019) Product Identification System Trademarks Worldwide Sales and Service