Product Brief PIC16(L)F1885X/7X (Microchip) - 5
| 制造商 | Microchip |
| 描述 | Full-Featured 28/40-Pin Microcontroller |
| 页数 / 页 | 16 / 5 — PIC16(L)F1885X/7X. Pin Diagram – 40-Pin PDIP Note 1: |
| 文件格式/大小 | PDF / 184 Kb |
| 文件语言 | 英语 |
PIC16(L)F1885X/7X. Pin Diagram – 40-Pin PDIP Note 1:
该数据表的模型线
- PIC16F18857-E/ML PIC16F18857-E/MLVAO PIC16F18857-E/SO PIC16F18857-E/SP PIC16F18857-E/SS PIC16F18857-E/SSVAO PIC16F18857-I/ML PIC16F18857-I/SO PIC16F18857-I/SP PIC16F18857-I/SS PIC16F18857-I/SSVAO PIC16F18857T-E/MLVAO PIC16F18857T-E/SS PIC16F18857T-E/SSVAO PIC16F18857T-I/ML PIC16F18857T-I/SO PIC16F18857T-I/SS PIC16F18857T-I/SSC02 PIC16F18857T-I/SSVAO PIC16LF18857-E/ML PIC16LF18857-E/SO PIC16LF18857-E/SP PIC16LF18857-E/SS PIC16LF18857-I/ML PIC16LF18857-I/SO PIC16LF18857-I/SP PIC16LF18857-I/SS PIC16LF18857T-I/ML PIC16LF18857T-I/SO PIC16LF18857T-I/SS
- PIC16F18877-E/ML PIC16F18877-E/MV PIC16F18877-E/MVVAO PIC16F18877-E/P PIC16F18877-E/PT PIC16F18877-I/ML PIC16F18877-I/MV PIC16F18877-I/P PIC16F18877-I/PREL PIC16F18877-I/PT PIC16F18877T-E/MV PIC16F18877T-E/MVVAO PIC16F18877T-I/ML PIC16F18877T-I/MV PIC16F18877T-I/PT PIC16LF18877-E/ML PIC16LF18877-E/MV PIC16LF18877-E/P PIC16LF18877-E/PT PIC16LF18877-I/ML PIC16LF18877-I/MV PIC16LF18877-I/MVC04 PIC16LF18877-I/P PIC16LF18877-I/PT PIC16LF18877T-I/MV PIC16LF18877T-I/MVC04 PIC16LF18877T-I/PT PIC16LF18877T-I/PTC01 PIC16LF18877T-I/PTRA3
文件文字版本
PIC16(L)F1885X/7X
Pin Diagram – 40-Pin PDIP Note 1:
2: VPP/MCLR/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 37 RB4 5 36 RB3 RA4 6 35 RB2 RA5
RE0 7 34 RB1
RB0 RE1 9 PIC16(L)F18875/18876/18877 4 RA3 8 33
32 VDD 31 VSS 30 RD7 29 RD6 28 RD5 27 RD4 26 RC7 16 25 RC6 17 24 RC5 18 23 RD0 19 22 RC4
RD3 RD1 20 21 RD2 RE2 10 VDD 11 VSS 12 RA7 13 RA6 14 RC0 15 RC1
RC2
RC3 See Table 4 for location of all peripheral function.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality. 44
43
42
41
40
39
38
37
36
35
34 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC Pin Diagram – 44-Pin TQFP C
16
1
)F
(L
88
75
/1
88
76
/1
88 2: NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4 NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
AN0/RA0
RA1
RA2
RA3 NC
Note 1: 33
32
31
30
29
28
27
26
25
24
23 12
13
14
15
16
17
18
19
20
21
22 77 RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3 1
2
3
4
5
6
7
8
9
10
11 PI RC7
RD4 See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality. 2014 Microchip Technology Inc. Advance Information DS40001768A-page 5
Pin Diagram – 40-Pin PDIP Note 1:
2: VPP/MCLR/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 37 RB4 5 36 RB3 RA4 6 35 RB2 RA5
RE0 7 34 RB1
RB0 RE1 9 PIC16(L)F18875/18876/18877 4 RA3 8 33
32 VDD 31 VSS 30 RD7 29 RD6 28 RD5 27 RD4 26 RC7 16 25 RC6 17 24 RC5 18 23 RD0 19 22 RC4
RD3 RD1 20 21 RD2 RE2 10 VDD 11 VSS 12 RA7 13 RA6 14 RC0 15 RC1
RC2
RC3 See Table 4 for location of all peripheral function.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality. 44
43
42
41
40
39
38
37
36
35
34 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC Pin Diagram – 44-Pin TQFP C
16
1
)F
(L
88
75
/1
88
76
/1
88 2: NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4 NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
AN0/RA0
RA1
RA2
RA3 NC
Note 1: 33
32
31
30
29
28
27
26
25
24
23 12
13
14
15
16
17
18
19
20
21
22 77 RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3 1
2
3
4
5
6
7
8
9
10
11 PI RC7
RD4 See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality. 2014 Microchip Technology Inc. Advance Information DS40001768A-page 5