Datasheet 48L256 (Microchip) - 9

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48L256 4.0 FUNCTIONAL DESCRIPTION
The 48L256 supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data is The 48L256 is controlled by a set of instructions that always latched in on the rising edge of SCK and are sent from a host controller, commonly referred to as always output on the falling edge of SCK. The only the SPI Master. The SPI Master communicates with the difference between SPI Modes 0 and 3 is the polarity 48L256 via the SPI bus which is comprised of four of the SCK signal when in the Inactive state (when the signal lines: SPI Master is in Standby mode and not transferring • Chip Select (CS) any data). SPI Mode 0 is defined as a low SCK while • Serial Clock (SCK) CS is not asserted (high) and SPI Mode 3 has SCK high in the Inactive state. The SCK Idle state must • Serial Input (SI) match when the CS is deasserted both before and • Serial Output (SO) after the communication sequence in SPI Mode 0 and The SPI protocol defines a total of four modes of 3. operation (Mode 0, 1, 2 or 3) with each mode differing The figures in this document depict Mode 0 with a in respect to the SCK polarity and phase and how the solid line on SCK while CS is inactive and Mode 3 with polarity and phase control the flow of data on the SPI a dotted line. bus.
FIGURE 4-1: SPI MODE 0 AND MODE 3
CS Mode 3 Mode 3 SCK Mode 0 Mode 0 SI MSb LSb SO MSb LSb
4.1 Interfacing the 48L256 on the SPI
4.1.2 SENDING DATA TO THE DEVICE
Bus
The 48L256 uses the Serial Data Input (SI) pin to receive information. All instructions, addresses and Communication to and from the 48L256 must be data input bytes are clocked into the device with the initiated by the SPI Master device. The SPI Master device must generate the serial clock for the 48L256 on Most Significant bit (MSb) first. the SCK pin. The 48L256 always operates as a slave The SI pin samples on the first rising edge of the SCK due to the fact that the Serial Clock pin (SCK) is always line after the CS has been asserted. an input. 4.1.3 RECEIVING DATA FROM THE 4.1.1 SELECTING THE DEVICE DEVICE The 48L256 is selected when the CS pin is low. When Data output from the device is transmitted on the Serial the device is not selected, data will not be accepted via Data Output (SO) pin with the MSb output first. The SO the SI pin and the SO pin will remain in a data is latched on the falling edge of the first SCK clock high-impedance state. cycle after the instruction has been clocked into the device, such as the Read from Memory Array and Read STATUS Register instructions. See
Section 6.0 “STATUS Register”
for more details.  2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 9 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service