Datasheet STPMIC1 (STMicroelectronics)

STPMIC1
Datasheet Highly integrated power management IC for micro processor units
Features
• Input voltage range from 2.8 V to 5.5 V • 4 adjustable general purpose LDOs • 1 LDO for DDR3 termination (sink-source), bypass mode for low power DDR or as general purpose LDO • 1 LDO for USB PHY supply with automatic power source detection • 1 reference voltage LDO for DDR memory • 4 adjustable adaptive constant on-time (COT) buck SMPS converters • 5.2 V / 1.1 A boost SMPS with bypass mode for 5 V input or battery input • 1 power switch 500 mA USB OTG compliant • 1 power switch 500 mA/1000 mA general purpose • User programmable non-volatile memory (NVM), enabling scalability to support a wide range of applications • I²C and digital IO control interface • WFQFN 44L (5x6x0.8)
Applications
• Power management for embedded micro processor units • Wearable and IoT • Portable devices • Man-machine interfaces
Product status link
• Smart home STPMIC1 • Power management unit companion chip of the STM32MP1 MPU
Device summary Description
STPMIC1APQR The STPMIC1 is a fully integrated power management IC designed for products
Order code
STPMIC1BPQR based on high integrated application processor designs requiring low power and high STPMIC1CPQR efficiency. WFQFN 44L The device integrates advanced low power features controlled by a host processor
Packing
via I²C and IO interface. (5x6x0.8) The STPMIC1 regulators are designed to supply power to the application processor as well as to the external system peripherals such as: DDR, Flash memories and other system devices. The boost converter can power up to 3 USB ports (two 500 mA host USB and one 100 mA USB OTG). Its advanced bypass architecture allows the smooth regulation of VBUS for USB ports from a battery as well as low-cost consumer 5 V AC-DC adapters. 4 buck SMPS are optimized to provide an excellent transient response and an output voltage precision for a wide range of operating conditions, high full range efficiency (η up to 90%) by implementing a low power mode with a smooth transition from PFM to PWM and also an advanced PWM synchronization technique with an integrated PLL for a better noise (EMI performance).
DS12792
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Rev 2
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October 2019
www.st.com For further information contact your local STMicroelectronics sales office. Document Outline Features Applications Description 1 Device configuration table 2 Typical application schematic 2.1 Recommended external components 2.2 Pinout and pin description 3 Electrical and timing characteristics 3.1 Absolute maximum ratings 3.2 Thermal characteristics 3.3 Consumption in typical application scenarios 3.4 Electrical and timing parameters 3.5 Application board curves 4 Power regulators and switch description 4.1 Overview 4.2 LDO regulators 4.2.1 LDO regulators - common features 4.2.2 LDO regulators - special features 4.2.3 LDO output voltage settings 4.3 DDR memory sub-system examples 4.3.1 Powering lpDDR2/lpDDR3 memory 4.3.2 Powering DDR3/DDR3L memory 4.4 Buck converters 4.4.1 BUCK general description 4.4.2 BUCK output voltage settings 4.5 Boost converter and power switches 4.5.1 Boost converter 4.5.2 PWR_USB_SW and PWR_SW power switches 4.6 USB sub-system examples 5 Functional description 5.1 Overview 5.2 Functional state machine 5.2.1 Main state machine diagram 5.2.2 State explanations 5.3 POWER_UP, POWER_DOWN sequence 5.4 Feature description 5.4.1 VIN conditions and monitoring 5.4.2 Turn-ON conditions 5.4.3 Turn-OFF conditions and restart_request 5.4.4 Reset and mask_reset option 5.4.5 Power control modes (MAIN / ALTERNATE) 5.4.6 Thermal protection 5.4.7 Overcurrent protection (OCP) 5.4.8 BOOST overvoltage protection 5.4.9 Watchdog feature 5.5 Programming 5.5.1 I2C interface 5.5.2 Non-volatile memory (NVM) 6 Register description 6.1 User register map 6.2 Status registers 6.2.1 Turn-ON status register (TURN_ON_SR) 6.2.2 Turn-OFF status register (TURN_OFF_SR) 6.2.3 Overcurrent protection LDO turn-OFF status register (OCP_LDOS_SR) 6.2.4 Overcurrent protection buck turn-OFF status register (OCP_BUCKS_BSW_SR) 6.2.5 Restart status register (RESTART_SR) 6.2.6 Version status register (VERSION_SR) 6.3 Control registers 6.3.1 Main control register (MAIN_CR) 6.3.2 Pads pull control register (PADS_PULL_CR) 6.3.3 Bucks pull-down control register (BUCKS_PD_CR) 6.3.4 LDO1-4 pull-down control register (LDO14_PD_CR) 6.3.5 LDO5/6 pull-down control register (LDO56_VREF_PD_CR) 6.3.6 PWR_SWOUT and VIN control register (SW_VIN_CR) 6.3.7 PONKEYn turn-OFF control register (PKEY_TURNOFF_CR) 6.3.8 Mask reset Buck control register (BUCKS_MRST_CR) 6.3.9 Mask reset LDO control register (LDOS_MRST_CR) 6.3.10 Watchdog control register (WDG_CR) 6.3.11 Watchdog timer control register (WDG_TMR_CR) 6.3.12 Bucks OCP turn-OFF control register (BUCKS_OCPOFF_CR) 6.3.13 LDO OCP turn-OFF control register (LDOS_OCPOFF_CR) 6.4 Power supplies control registers 6.4.1 BUCKx MAIN mode control registers (BUCKx_MAIN_CR) (x=1…4) 6.4.2 REFDDR MAIN mode control register (REFDDR_MAIN_CR) 6.4.3 LDOx MAIN mode control registers (LDOx_MAIN_CR) (x=1, 2, 5, 6) 6.4.4 LDO3 MAIN mode control register (LDO3_MAIN_CR) 6.4.5 LDO4 MAIN mode control register (LDO4_MAIN_CR) 6.4.6 BUCKx ALTERNATE mode control registers (BUCKx_ALT_CR)(x=1..4) 6.4.7 REFDDR ALTERNATE mode control register (REFDDR_ALT_CR) 6.4.8 LDOx ALTERNATE mode control registers (LDOx_ALT_CR) (x=1, 2, 5, 6) 6.4.9 LDO3 ALTERNATE mode control register (LDO3_ALT_CR) 6.4.10 LDO4 ALTERNATE mode control register (LDO4_ALT_CR) 6.4.11 Boost/switch control register (BST_SW_CR) 6.5 Interrupt registers 6.5.1 Overall interrupt register behavior 6.5.2 Interrupt pending register 1 (INT_PENDING_R1) 6.5.3 Interrupt pending register 2 (INT_PENDING_R2) 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) 6.5.6 Interrupt debug latch registers (INT_DBG_LATCH_Rx) 6.5.7 Interrupt clear registers (INT_CLEAR_Rx) 6.5.8 Interrupt mask registers (INT_MASK_Rx) 6.5.9 Interrupt set mask registers (INT_SET_MASK_Rx) 6.5.10 Interrupt clear mask registers (INT_CLEAR_MASK_Rx) 6.5.11 Interrupt source register 1 (INT_SRC_R1) 6.5.12 Interrupt source register 2 (INT_SRC_R2) 6.5.13 Interrupt source register 3 ( INT_SRC_R3) 6.5.14 Interrupt source register 4 ( INT_SRC_R4) 6.6 NVM registers 6.6.1 NVM status register (NVM_SR) 6.6.2 NVM control register (NVM_CR) 6.7 NVM shadow registers 6.7.1 NVM main control shadow register (NVM_MAIN_CTRL_SHR) 6.7.2 NVM BUCK rank shadow register (NVM_BUCKS_RANK_SHR) 6.7.3 NVM LDOs rank shadow register 1 (NVM_LDOS_RANK_SHR1) 6.7.4 NVM LDOs rank shadow register 2 (NVM_LDOS_RANK_SHR2) 6.7.5 NVM BUCKs voltage output shadow register (NVM_BUCKS_VOUT_SHR) 6.7.6 NVM LDOs voltage output shadow register 1 (NVM_LDOS_VOUT_SHR1 6.7.7 NVM LDOs voltage output shadow register 2 (NVM_LDOS_VOUT_SHR2) 6.7.8 NVM device address shadow register (I2C_ADDR_SHR) 7 Package information 7.1 WFQFN 44L (5X6X0.8) package information 8 Marking composition 9 Ordering information Revision history