Datasheet STPMIC1 (STMicroelectronics) - 3

STPMIC1 Typical application schematic 2 Typical application schematic Figure 1. Typical application schematic
(VIN from 2.8V to 5.5V DC)
BUCK1IN
LX1 VIN
VLX1
BUCK1 VDD_CORE CBUCK1IN
VOUT1 PGND1
(SMPS) CVOUT1
BUCK2IN
LX2
VLX2
BUCK2 VDD_DDR CBUCK2IN
VOUT2
(DDR3, DDR3L,
PGND2
(SMPS) CVOUT2 lpDDR2, lpDDR3, DDR4)
BUCK3IN
LX3
VLX3
BUCK3 VDD CBUCK3IN
VOUT3
(VIO: 1V8 or 3V3)
PGND3
(SMPS) CVOUT3
BUCK4IN
LX4
VLX4
BUCK4 VDD_AUX CBUCK4IN
VOUT4
(to system devices
PGND4
(SMPS) CVOUT4 or CPU voltage) LXB
VLXBST
BOOST
BSTOUT
CVLXBST VIN BYPASS
PGND5
CBSTOUT
VBUSOTG
PWR_USB_SW VBUS_OTG CVBUSOTG (close to USB connector)
SWIN
BSTOUT PWR_SW
SWOUT
VBUS_HOST CSWOUT close to USB BSTOUT connector) SUPPLY
LDO4OUT
VBUSOTG LDO4
VIN
VDD_USB MUX (fixed 3.3V to CLDO4OUT AP USB PHY ) CVIN
INTLDO
INTLDO
LDO3IN
CINTLDO
AGND
VDD_DDR CLDO3IN LDO3 (normal,
LDO3OUT
VTT_DDR3
VIO
NVM bypass, (to DDR3/3L VDD DDRVTT) CLDO3OUTterminations or to
SCL
lpDDR2/3 VDD1) BUCK2IN I2C
SDA
DDR_REF
VREFDDR
ain VREF_DDR (VOUT2/2)
INTn
om CVREF to / from d REGISTER host AP
PWRCTRL
VIO
LDO1OUT
STATE LDO1 VOUT_LDO1
RSTn
MACHINE (to system device) CLDO1OUT POWER
WAKEUP
SUPPLIES CONTROL user push button
LDO6OUT
LDO6
PONKEYn
VOUT_LDO6 LOGIC (to system device) CLDO6OUT SYSTEM CONTROL
LDO16IN LDO2OUT
VIN LDO2 VOUT_LDO2 (to Flash Memory CLDO16IN CLDO2OUT or system device)
LDO25IN LDO5OUT
LDO5 VOUT_LDO5 (to SD-Card or CLDO25IN CLDO5OUT
GNDLDO EPGND
system device) christophe belet ST Note: BUCK1IN and BUCK2IN must always be connected to VIN
DS12792
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Rev 2 page 3/141
Document Outline Features Applications Description 1 Device configuration table 2 Typical application schematic 2.1 Recommended external components 2.2 Pinout and pin description 3 Electrical and timing characteristics 3.1 Absolute maximum ratings 3.2 Thermal characteristics 3.3 Consumption in typical application scenarios 3.4 Electrical and timing parameters 3.5 Application board curves 4 Power regulators and switch description 4.1 Overview 4.2 LDO regulators 4.2.1 LDO regulators - common features 4.2.2 LDO regulators - special features 4.2.3 LDO output voltage settings 4.3 DDR memory sub-system examples 4.3.1 Powering lpDDR2/lpDDR3 memory 4.3.2 Powering DDR3/DDR3L memory 4.4 Buck converters 4.4.1 BUCK general description 4.4.2 BUCK output voltage settings 4.5 Boost converter and power switches 4.5.1 Boost converter 4.5.2 PWR_USB_SW and PWR_SW power switches 4.6 USB sub-system examples 5 Functional description 5.1 Overview 5.2 Functional state machine 5.2.1 Main state machine diagram 5.2.2 State explanations 5.3 POWER_UP, POWER_DOWN sequence 5.4 Feature description 5.4.1 VIN conditions and monitoring 5.4.2 Turn-ON conditions 5.4.3 Turn-OFF conditions and restart_request 5.4.4 Reset and mask_reset option 5.4.5 Power control modes (MAIN / ALTERNATE) 5.4.6 Thermal protection 5.4.7 Overcurrent protection (OCP) 5.4.8 BOOST overvoltage protection 5.4.9 Watchdog feature 5.5 Programming 5.5.1 I2C interface 5.5.2 Non-volatile memory (NVM) 6 Register description 6.1 User register map 6.2 Status registers 6.2.1 Turn-ON status register (TURN_ON_SR) 6.2.2 Turn-OFF status register (TURN_OFF_SR) 6.2.3 Overcurrent protection LDO turn-OFF status register (OCP_LDOS_SR) 6.2.4 Overcurrent protection buck turn-OFF status register (OCP_BUCKS_BSW_SR) 6.2.5 Restart status register (RESTART_SR) 6.2.6 Version status register (VERSION_SR) 6.3 Control registers 6.3.1 Main control register (MAIN_CR) 6.3.2 Pads pull control register (PADS_PULL_CR) 6.3.3 Bucks pull-down control register (BUCKS_PD_CR) 6.3.4 LDO1-4 pull-down control register (LDO14_PD_CR) 6.3.5 LDO5/6 pull-down control register (LDO56_VREF_PD_CR) 6.3.6 PWR_SWOUT and VIN control register (SW_VIN_CR) 6.3.7 PONKEYn turn-OFF control register (PKEY_TURNOFF_CR) 6.3.8 Mask reset Buck control register (BUCKS_MRST_CR) 6.3.9 Mask reset LDO control register (LDOS_MRST_CR) 6.3.10 Watchdog control register (WDG_CR) 6.3.11 Watchdog timer control register (WDG_TMR_CR) 6.3.12 Bucks OCP turn-OFF control register (BUCKS_OCPOFF_CR) 6.3.13 LDO OCP turn-OFF control register (LDOS_OCPOFF_CR) 6.4 Power supplies control registers 6.4.1 BUCKx MAIN mode control registers (BUCKx_MAIN_CR) (x=1…4) 6.4.2 REFDDR MAIN mode control register (REFDDR_MAIN_CR) 6.4.3 LDOx MAIN mode control registers (LDOx_MAIN_CR) (x=1, 2, 5, 6) 6.4.4 LDO3 MAIN mode control register (LDO3_MAIN_CR) 6.4.5 LDO4 MAIN mode control register (LDO4_MAIN_CR) 6.4.6 BUCKx ALTERNATE mode control registers (BUCKx_ALT_CR)(x=1..4) 6.4.7 REFDDR ALTERNATE mode control register (REFDDR_ALT_CR) 6.4.8 LDOx ALTERNATE mode control registers (LDOx_ALT_CR) (x=1, 2, 5, 6) 6.4.9 LDO3 ALTERNATE mode control register (LDO3_ALT_CR) 6.4.10 LDO4 ALTERNATE mode control register (LDO4_ALT_CR) 6.4.11 Boost/switch control register (BST_SW_CR) 6.5 Interrupt registers 6.5.1 Overall interrupt register behavior 6.5.2 Interrupt pending register 1 (INT_PENDING_R1) 6.5.3 Interrupt pending register 2 (INT_PENDING_R2) 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) 6.5.6 Interrupt debug latch registers (INT_DBG_LATCH_Rx) 6.5.7 Interrupt clear registers (INT_CLEAR_Rx) 6.5.8 Interrupt mask registers (INT_MASK_Rx) 6.5.9 Interrupt set mask registers (INT_SET_MASK_Rx) 6.5.10 Interrupt clear mask registers (INT_CLEAR_MASK_Rx) 6.5.11 Interrupt source register 1 (INT_SRC_R1) 6.5.12 Interrupt source register 2 (INT_SRC_R2) 6.5.13 Interrupt source register 3 ( INT_SRC_R3) 6.5.14 Interrupt source register 4 ( INT_SRC_R4) 6.6 NVM registers 6.6.1 NVM status register (NVM_SR) 6.6.2 NVM control register (NVM_CR) 6.7 NVM shadow registers 6.7.1 NVM main control shadow register (NVM_MAIN_CTRL_SHR) 6.7.2 NVM BUCK rank shadow register (NVM_BUCKS_RANK_SHR) 6.7.3 NVM LDOs rank shadow register 1 (NVM_LDOS_RANK_SHR1) 6.7.4 NVM LDOs rank shadow register 2 (NVM_LDOS_RANK_SHR2) 6.7.5 NVM BUCKs voltage output shadow register (NVM_BUCKS_VOUT_SHR) 6.7.6 NVM LDOs voltage output shadow register 1 (NVM_LDOS_VOUT_SHR1 6.7.7 NVM LDOs voltage output shadow register 2 (NVM_LDOS_VOUT_SHR2) 6.7.8 NVM device address shadow register (I2C_ADDR_SHR) 7 Package information 7.1 WFQFN 44L (5X6X0.8) package information 8 Marking composition 9 Ordering information Revision history