Datasheet ST7LITEUSx (STMicroelectronics) - 10
| 制造商 | STMicroelectronics |
| 描述 | 8-bit MCU with single voltage Flash memory, ADC, timers. ST7ULTRALITE (ST7LITEUS2, ST7LITEUS5) |
| 页数 / 页 | 108 / 10 — ST7LITEUSx. Register. Address. Block. Register Name. Reset Status. … |
| 文件格式/大小 | PDF / 889 Kb |
| 文件语言 | 英语 |
ST7LITEUSx. Register. Address. Block. Register Name. Reset Status. Remarks. Label. Notes
该数据表的模型线
- ST7FLITEUS2B3 ST7FLITEUS2B6 ST7FLITEUS2M3 ST7FLITEUS2M3TR ST7FLITEUS2M6 ST7FLITEUS2M6TR ST7FLITEUS2U3TR ST7FLITEUS2U6TR ST7FLITEUS5B3 ST7FLITEUS5B6 ST7FLITEUS5M3 ST7FLITEUS5M3TR ST7FLITEUS5M6 ST7FLITEUS5M6TR ST7FLITEUS5U3 ST7FLITEUS5U3TR ST7FLITEUS5U6 ST7FLITEUS5U6TR ST7FLITEUSICD ST7PLITEUS2B3 ST7PLITEUS2B6 ST7PLITEUS2M3 ST7PLITEUS2M3TR ST7PLITEUS2M6 ST7PLITEUS2M6TR ST7PLITEUS2U3TR ST7PLITEUS2U6TR ST7PLITEUS5B3 ST7PLITEUS5B6 ST7PLITEUS5M3 ST7PLITEUS5M3TR ST7PLITEUS5M6 ST7PLITEUS5M6TR ST7PLITEUS5U3 ST7PLITEUS5U3TR ST7PLITEUS5U6 ST7PLITEUS5U6TR
文件文字版本
ST7LITEUSx Register Address Block Register Name Reset Status Remarks Label
0047h MuxIO- MUXCR0 Mux IO-Reset Control Register 0 00h R/W 0048h reset MUXCR1 Mux IO-Reset Control Register 1 00h R/W 0049h AWUPR AWU Prescaler Register FFh R/W AWU 004Ah AWUCSR AWU Control/Status Register 00h R/W 004Bh DMCR DM Control Register 00h R/W 004Ch DMSR DM Status Register 00h R/W 004Dh DMBK1H DM Breakpoint Register 1 High 00h R/W DM 3) 004Eh DMBK1L DM Breakpoint Register 1 Low 00h R/W 004Fh DMBK2H DM Breakpoint Register 2 High 00h R/W 0050h DMBK2L DM Breakpoint Register 2 Low 00h R/W 0051h to Reserved area (47 bytes) 007Fh Legend: x=undefined, R/W=read/write
Notes
:
1.
The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents.
2.
The bits associated with unavailable pins must always keep their reset value.
3.
For a description of the DM registers, see the ST7 ICC Protocol Reference Manual. 10/108 1
0047h MuxIO- MUXCR0 Mux IO-Reset Control Register 0 00h R/W 0048h reset MUXCR1 Mux IO-Reset Control Register 1 00h R/W 0049h AWUPR AWU Prescaler Register FFh R/W AWU 004Ah AWUCSR AWU Control/Status Register 00h R/W 004Bh DMCR DM Control Register 00h R/W 004Ch DMSR DM Status Register 00h R/W 004Dh DMBK1H DM Breakpoint Register 1 High 00h R/W DM 3) 004Eh DMBK1L DM Breakpoint Register 1 Low 00h R/W 004Fh DMBK2H DM Breakpoint Register 2 High 00h R/W 0050h DMBK2L DM Breakpoint Register 2 Low 00h R/W 0051h to Reserved area (47 bytes) 007Fh Legend: x=undefined, R/W=read/write
Notes
:
1.
The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents.
2.
The bits associated with unavailable pins must always keep their reset value.
3.
For a description of the DM registers, see the ST7 ICC Protocol Reference Manual. 10/108 1