Datasheet ST7LITEUSx (STMicroelectronics) - 2

制造商STMicroelectronics
描述8-bit MCU with single voltage Flash memory, ADC, timers. ST7ULTRALITE (ST7LITEUS2, ST7LITEUS5)
页数 / 页108 / 2 — ST7LITEUSx. ST7LITEUSx . 1 ST7LITEUSx. 1 INTRODUCTION. .. . ... . 1. . 4. …
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ST7LITEUSx. ST7LITEUSx . 1 ST7LITEUSx. 1 INTRODUCTION. .. . ... . 1. . 4. 2 IN. PITRO. N D DUCTI. ESCRI ON. PTIO .. N .. 3 PI. R N D. EGI ESCRIPTIO

ST7LITEUSx ST7LITEUSx  1 ST7LITEUSx 1 INTRODUCTION .  ..  1  4 2 IN PITRO N D DUCTI ESCRI ON PTIO . N . 3 PI R N D EGI ESCRIPTIO

该数据表的模型线

文件文字版本

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ST7LITEUSx ST7LITEUSx . 1 ST7LITEUSx 1 INTRODUCTION . . . . . .. . . 1 . 4 1 2 IN PITRO N D DUCTI ESCRI ON PTIO . . N . . . 4 5 2 3 PI R N D EGI ESCRIPTIO STER & ME N M . O . . R . Y . . M . A . . P . . . 5 8 3 4 REGISTER & FLASH PRO M G EMO RAM R M Y E M M A O P . RY . 8 11 4 FLASH
4.1 I
PRO
NTR
G
OD
RAM M
UCTIO
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RY
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. 11 4.1 2 IN M TRO AIN DUCTION . FEATURES . 11 . 11 4.2 3 M P AIN RO FEATURES GRAMMING . M . O . DES . 11 . 11 4.3 4 P I RO CC G I R N AMMING M TERFACE . O . .DES . 11 12 4.4 5 IC M C IN EM TERFACE ORY PR . OTECTI . ON . 12 13 4.5 6 M R EM EL ORY PR ATED OTECTI DOCUM ON EN . TATI . ON . 13 4.6 7 RELATED EGIS DO TER CUM DE EN SCRI TATI PTIONON . 13 4.
5 CE
7 REGIS
NTRAL
TER DESCRIPTION
PROCESSING UNIT
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14 5 CENTRAL
5.1 INTR
PROCESSING UNIT
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. 14 5.1 2 IN M TRO AIN DUCTION . FEATURES . 14 . 14 5.2 3 M C AIN PU FEATURES REGISTE RS . 14 5.
6 SU
3 CPU
PPLY,
REGISTE
RESET A
RS
ND
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CLOC
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K MAN
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GEME
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. 14
. 17 6 SUPPLY,
6.1 INT
RESET A
ERNAL R
ND
C O
CLOC
SCILL
K MAN
ATOR
AGEME
ADJU
NT
STME
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17
6.1 2 IN R TE EG RNAL IS R TER C O DE SCI SCRI LLATOR PTION . ADJ . U . STM . E . NT . 17 19 6.2 3 REG ES ISTER DE ET SEQ SCRI UENC PTION E MA NA . GER . (R . SM . ) . 19 22 6.3 4 RESET SEQ EGISTER UENC DE E M SCRI ANA PTION GER . (R . SM . ) . 22 24
7 I
6.
N
4 REG
TERRU
ISTER
PTS .
DE
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SCRI
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PTION
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25 7 INTERRU
7.1 N
PTS
ON MA
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SKABLE SOFTW
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7.1 7.2 NON MA EXTER SKABLE SOFTW NAL INTER A RUPTS RE . .INTERR . UPT . 25 7.2 3 EXTER PER NAL IPHER IN AL TERRUPTS INTER . RUPTS . 25 7.3 7.4 PERIPHERAL INTERRUPTS SYSTEM INTEGRITY MANA . GE . ME . NT (S . I) . 25 28
8
7.4
PO
SYSTEM INTEGRITY
WER SAVING MODES
MAN
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33 8 PO
8.
WER
1 IN
SA
TR
VING
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UCTIO
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. 33 8.1 2 IN S T L R O O W DUCTIO MODE N . 34 . 33 8.2 3 SL W O AI W M T M O O D D E E . 34 34 8.3 4 W A AIT M CTI OD VE-H E A . LT . AND . HAL . T . M . O . DE . S . 35 8.4 8.5 ACTIVE-H UTO W ALT AND AKE UP HALT FROM MODES . HALT MOD . E . 36 37
9 I/
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RTS . .
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41 9 I/O PO
9.1 I
RTS
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. 41 9.1 2 IN F TRO UNC DUCTIO TIONAL N . DESC . RIPTI . O . N . 42 . 41 9.2 3 FUNC UNU TION SED AL I/O DESC PINS RIPTI . O . N . 42 . 45 9.3 4 U L NUSED OW PO I/O P WER INS MO . DE . S . 46 . 45 9.4 9.5 L I OW NTE POWER RRUPTS MO DE . S . 46 45 9.5 9.6 IN I/ T O E RRUP PORT TS IM PL . EM . ENTATIO . N . 46 45
10
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I/
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O POR
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T IM
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PLEM
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ENTATIO
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