Datasheet BLP05H9S500P (Ampleon) - 3
| 制造商 | Ampleon |
| 描述 | Power LDMOS transistor |
| 页数 / 页 | 13 / 3 — BLP05H9S500P. Power LDMOS transistor. 6. Characteristics. Table 6. DC … |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
BLP05H9S500P. Power LDMOS transistor. 6. Characteristics. Table 6. DC characteristics. Symbol Parameter. Conditions. Min. Typ. Max Unit
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BLP05H9S500P Power LDMOS transistor 6. Characteristics Table 6. DC characteristics
Tj = 25 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 1.8 mA 108 - - V VGS(th) gate-source threshold voltage VDS = 10 V; ID = 180 mA 1.5 2.1 2.5 V IDSS drain leakage current VGS = 0 V; VDS = 50 V - - 2.8 A IDSX drain cut-off current VGS = VGS(th) + 3.75 V; - 31 - A VDS = 10 V IGSS gate leakage current VGS = 11 V; VDS = 0 V - - 280 nA gfs forward transconductance VDS = 10 V; ID = 9 A - 13 - S RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V; - 0.12 - ID = 6.3 A
Table 7. RF characteristics
Test signal: CW pulsed (tp = 100 s; = 10 %); f = 443 MHz; RF performance at VDS = 50 V; IDq = 100 mA; Tcase = 25 C; unless otherwise specified; in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gp power gain PL = 500 W 24 25.2 - dB RLin input return loss PL = 500 W - 14.5 9 dB D drain efficiency PL = 500 W 68 72 - %
7. Test information 7.1 Ruggedness in class-AB operation
The BLP05H9S500P is capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: VDS = 50 V; IDq = 50 mA; PL = 500 W (CW).
7.2 Impedance information Table 8. Typical impedance
Measured load-pull ZS and ZL device impedances per section; IDq = 25 mA per section; VDS = 50 V; typical values unless otherwise specified.
f ZS [1] ZL [1] (MHz) ( ) ( )
433 1.3 2.1j 2.8 + 2.4j [1] ZS and ZL defined in Figure 1. BLP05H9S500P All information provided in this document is subject to legal disclaimers. © Ampleon Netherlands B.V. 2019. All rights reserved.
Product data sheet Rev. 1 — 10 September 2019 3 of 13
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Test information 7.1 Ruggedness in class-AB operation 7.2 Impedance information 7.3 Application circuit 7.4 Graphical data 8. Package outline 9. Handling information 10. Abbreviations 11. Revision history 12. Legal information 12.1 Data sheet status 12.2 Definitions 12.3 Disclaimers 12.4 Trademarks 13. Contact information 14. Contents
BLP05H9S500P Power LDMOS transistor 6. Characteristics Table 6. DC characteristics
Tj = 25 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 1.8 mA 108 - - V VGS(th) gate-source threshold voltage VDS = 10 V; ID = 180 mA 1.5 2.1 2.5 V IDSS drain leakage current VGS = 0 V; VDS = 50 V - - 2.8 A IDSX drain cut-off current VGS = VGS(th) + 3.75 V; - 31 - A VDS = 10 V IGSS gate leakage current VGS = 11 V; VDS = 0 V - - 280 nA gfs forward transconductance VDS = 10 V; ID = 9 A - 13 - S RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V; - 0.12 - ID = 6.3 A
Table 7. RF characteristics
Test signal: CW pulsed (tp = 100 s; = 10 %); f = 443 MHz; RF performance at VDS = 50 V; IDq = 100 mA; Tcase = 25 C; unless otherwise specified; in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gp power gain PL = 500 W 24 25.2 - dB RLin input return loss PL = 500 W - 14.5 9 dB D drain efficiency PL = 500 W 68 72 - %
7. Test information 7.1 Ruggedness in class-AB operation
The BLP05H9S500P is capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: VDS = 50 V; IDq = 50 mA; PL = 500 W (CW).
7.2 Impedance information Table 8. Typical impedance
Measured load-pull ZS and ZL device impedances per section; IDq = 25 mA per section; VDS = 50 V; typical values unless otherwise specified.
f ZS [1] ZL [1] (MHz) ( ) ( )
433 1.3 2.1j 2.8 + 2.4j [1] ZS and ZL defined in Figure 1. BLP05H9S500P All information provided in this document is subject to legal disclaimers. © Ampleon Netherlands B.V. 2019. All rights reserved.
Product data sheet Rev. 1 — 10 September 2019 3 of 13
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Test information 7.1 Ruggedness in class-AB operation 7.2 Impedance information 7.3 Application circuit 7.4 Graphical data 8. Package outline 9. Handling information 10. Abbreviations 11. Revision history 12. Legal information 12.1 Data sheet status 12.2 Definitions 12.3 Disclaimers 12.4 Trademarks 13. Contact information 14. Contents