Datasheet STSPIN32F0601, STSPIN32F0602 (STMicroelectronics) - 5

STSPIN32F0601, STSPIN32F0602 Pin description and connection diagram Table 1. Legend/abbreviations used in the pin description table Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function Pin name during and after reset is the same as the actual pin name AO Gate Driver Analog Output P Gate Driver Supply \ GND pin Pin type S Supply pin I Input-only pin I/O Input / output pin FT 5 V-tolerant I/O FTf 5 V-tolerant I/O, FM+ capable TTa 3.3 V-tolerant I/O directly connected to ADC I/O structure TC Standard 3.3V I/O B Dedicated BOOT0 pin Bidirectional reset pin with embedded weak pull-up RST resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during Notes and after reset Alternate functions Functions selected through GPIOx_AFR registers Pin functions Functions directly selected/enabled through peripheral Additional functions registers
Table 2. Pin description N. Name Type Function
1 PB8 I/O - FTf MCU PB8 2 VSS Supply MCU digital ground 3 VDD Supply MCU digital power supply 4 PC13 I/O - TC MCU PC13 5 PC14 I/O - TC MCU PC14 6 PC15 I/O - TC MCU PC15 7 PF0 I/O - FT MCU PF0 8 PF1 I/O - FT MCU PF1 9 NRST I/O - RST MCU Reset pin 10 VSSA Supply MCU analog ground 11 VDDA Supply MCU analog power supply 12 PA0 I/O - TTa MCU PA0 13 PA1 I/O - TTa MCU PA1 DS12981 Rev 3 5/29 29 Document Outline 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F060x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history