Datasheet STSPIN32F0601, STSPIN32F0602 (STMicroelectronics) - 7

STSPIN32F0601, STSPIN32F0602 Pin description and connection diagram Table 2. Pin description (continued) N. Name Type Function
56 PA13 I/O - FT MCU PA13/SWDIO (System debug data) MCU PA14/SWDCLK (System debug 57 PA14 I/O - FT clock) 58 PA15 I/O - FT MCU PA15 59 PB3 I/O - FT MCU PB3 60 PB4 I/O - FT MCU PB4 61 PB5 I/O - FT MCU PB5 62 PB6 I/O - FTf MCU PB6 63 PB7 I/O - FTf MCU PB7 64 BOOT0 I - B Boot memory selection 32, 36, 37, 38, 39, 43, 44, 45, NC Not Connected 49 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low. When the EN is set low, gate driver outputs are forced low and assure low impedance.
Table 3. STSPIN32F060x MCU-Driver internal connections MCU pad Type Controller pad Function
PB12 I/O - FT FAULT Gate Driver Fault output PB13 I/O - FT LIN1 Gate Driver Low-Side input driver 1 PB14 I/O - FT LIN2 Gate Driver Low-Side input driver 2 PB15 I/O - FT LIN3 Gate Driver Low-Side input driver 3 PA8 I/O - FT HIN1 Gate Driver High-Side input driver 1 PA9 I/O - FTf HIN2 Gate Driver High-Side input driver 2 PA10 I/O - FTf HIN3 Gate Driver High-Side input driver 3 PA11 I/O - FT EN Gate Driver shutdown input Note: Each unused GPIO inside the SiP should be configured in OUTPUT mode low level after startup by software. DS12981 Rev 3 7/29 29 Document Outline 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F060x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history