Datasheet SSM2603 (Analog Devices) - 4

SSM2603 Data Sheet Parameter Min Typ Max Unit Conditions
HEADPHONE OUTPUT Full-Scale Output Voltage 1 × AVDD/3.3 V rms Maximum Output Power 30 mW RL = 32 Ω 60 mW RL = 16 Ω Signal-to-Noise Ratio (A-Weighted) 85 96 dB AVDD = 3.3 V 90 dB AVDD = 1.8 V THD + N −65 dB POUT = 10 mW −60 dB POUT = 20 mW Power Supply Rejection Ratio 50 dB Mute Attenuation 80 dB LINE INPUT TO LINE OUTPUT Full-Scale Output Voltage 1 × AVDD/3.3 V rms Signal-to-Noise Ratio (A-Weighted) 92 dB AVDD = 3.3 V 86 dB AVDD = 1.8 V THD + N −80 dB AVDD = 3.3 V −80 dB AVDD = 1.8 V Power Supply Rejection 50 dB MICROPHONE INPUT TO HEADPHONE OUTPUT Full-Scale Output Voltage 1 × AVDD/3.3 V rms Signal-to-Noise Ratio (A-Weighted) 94 dB AVDD = 3.3 V 88 dB AVDD = 1.8 V Power Supply Rejection Ratio 50 dB Programmable Attenuation 6 15 dB Gain Step 3 dB Mute Attenuation 80 dB 1 The line output is tested by sending a −1 dBFS input from the DAC to the line output.
DIGITAL FILTER CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Conditions
ADC FILTER Pass Band 0 0.445 fS Hz ±0.04 dB 0.5 fS Hz −6 dB Pass-Band Ripple ±0.04 dB Stop Band 0.555 fS Hz Stop-Band Attenuation −61 dB f > 0.567 fS High-Pass Filter Corner Frequency 3.7 Hz −3 dB 10.4 Hz −0.5 dB 21.6 Hz −0.1 dB DAC FILTER Pass Band 0 0.445 fS Hz ±0.04 dB 0.5 fS Hz −6 dB Pass-Band Ripple ±0.04 dB Stop Band 0.555 fS Hz Stop-Band Attenuation −61 dB f > 0.565 fS MASTER CLOCK TOLERANCE1 Frequency Range 8.0 18.5 MHz Jitter Tolerance 50 ps 1 CLKDIV2 bit (Register R8, Bit D6) is set to 0. Rev. D | Page 4 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide