Datasheet PI6CG33601C (Diodes) - 2
| 制造商 | Diodes |
| 描述 | 3.3V Very Low Power 6-Output PCIe Clock Generator With On-chip Termination |
| 页数 / 页 | 24 / 2 — PI6CG33601C. Pin Configuration. GND. Pin Description. Pin #. Pin Name. … |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
PI6CG33601C. Pin Configuration. GND. Pin Description. Pin #. Pin Name. Type. Description
该数据表的模型线
文件文字版本
A product Line of Diodes Incorporated
PI6CG33601C Pin Configuration
O O PD# V DD OE5# Q5- Q5+ OE4# Q4- Q4+ V DD V DD 40 39 38 37 36 35 34 33 32 31 SS_SEL_TRI 1 30 OE3# XTAL_IN/CLK 2 29 Q3- XTAL_OUT 3 28 Q3+ VDD_OSC 4 27 VDDO VDD_REFOUT 5 26 VDDA
GND
SADR/REFOUT 6 25 NC NC 7 24 OE2# GND_DIG 8 23 Q2- SCLK 9 22 Q2+ SDATA 10 21 OE1# 11 12 13 14 15 16 17 18 19 20 O O Q0+ Q0- Q1+ NC _DIG V DD OE0# VDD Q1- V DD V DD
Pin Description Pin # Pin Name Type Description
Latched select input to select spread spectrum amount at initial power up 1 SS_SEL_TRI Input Tri-level 1 = -0.5% spread, M = Spread Off, 0 = Spread Off. This pin has both in- ternal pull-up and pull-down. Refer to SMBUS byte_1 bit 4, 3 = '01' to get -0.25% spread. 2 XTAL_IN/CLK Input Crystal input or CMOS reference input 3 XTAL_OUT Output Crystal output 4 VDD_OSC Power Power supply for oscillator circuitry, nominal 3.3V 5 VDD_REFOUT Power Power supply for buffered CMOS output 6 SADR/REFOUT Input/ Output CMOS Latch to select SMBus Address or LVCMOS REFOUT. This pin has an internal pull-down 7, 20, 25 NC N/A No Connect 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V 12, 17, 27, 32, 39 VDDO Power Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 13 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 14 Q0+ Output HCSL Differential true clock output PI6CG33601C www.diodes.com January 2020 Document Number DS42295 Rev 3-2 2 Diodes Incorporated
PI6CG33601C Pin Configuration
O O PD# V DD OE5# Q5- Q5+ OE4# Q4- Q4+ V DD V DD 40 39 38 37 36 35 34 33 32 31 SS_SEL_TRI 1 30 OE3# XTAL_IN/CLK 2 29 Q3- XTAL_OUT 3 28 Q3+ VDD_OSC 4 27 VDDO VDD_REFOUT 5 26 VDDA
GND
SADR/REFOUT 6 25 NC NC 7 24 OE2# GND_DIG 8 23 Q2- SCLK 9 22 Q2+ SDATA 10 21 OE1# 11 12 13 14 15 16 17 18 19 20 O O Q0+ Q0- Q1+ NC _DIG V DD OE0# VDD Q1- V DD V DD
Pin Description Pin # Pin Name Type Description
Latched select input to select spread spectrum amount at initial power up 1 SS_SEL_TRI Input Tri-level 1 = -0.5% spread, M = Spread Off, 0 = Spread Off. This pin has both in- ternal pull-up and pull-down. Refer to SMBUS byte_1 bit 4, 3 = '01' to get -0.25% spread. 2 XTAL_IN/CLK Input Crystal input or CMOS reference input 3 XTAL_OUT Output Crystal output 4 VDD_OSC Power Power supply for oscillator circuitry, nominal 3.3V 5 VDD_REFOUT Power Power supply for buffered CMOS output 6 SADR/REFOUT Input/ Output CMOS Latch to select SMBus Address or LVCMOS REFOUT. This pin has an internal pull-down 7, 20, 25 NC N/A No Connect 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V 12, 17, 27, 32, 39 VDDO Power Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 13 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 14 Q0+ Output HCSL Differential true clock output PI6CG33601C www.diodes.com January 2020 Document Number DS42295 Rev 3-2 2 Diodes Incorporated