Datasheet PI6CB332000 (Diodes) - 10
| 制造商 | Diodes |
| 描述 | 20-Output PCIe G4 Clock Buffer With On-Chip Termination |
| 页数 / 页 | 21 / 10 — PI6CB332000. HCSL Output DC Characteristics. Symbol. Parameters. … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
PI6CB332000. HCSL Output DC Characteristics. Symbol. Parameters. Condition. Min. Typ. Max. Units. Note:. HCSL Output DC Test Load
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PI6CB332000 HCSL Output DC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
VOH Output Voltage High (1) 225 270 mV VOL Output Voltage Low (1) 10 0 150 mV VOMAX Output Voltage Maximum (Overshoot) (1) VOH + 75mV mV VOMIN Output Voltage Minimum (Undershoot) (1) VOL + 75mV mV Vcross absolute Absolute Crossing Point Voltage (1,2) 130 200 mV Vcross relative Relative Crossing Point Voltage (1,2) 35 mV DC Distor- tion Duty Cycle Distortion (3,4) -1 1 %
Note:
1. At default SMBUS amplitude settings. 2. Guaranteed by design and characterization—not 100% tested in production. 3. Measured from differential waveform. 4. Duty cycle distortion is the difference in duty cycle between the out and input clock when the device is operated in the PLL bypass mode.
HCSL Output DC Test Load
0.75V 85Ω R1 CK+ SMA 0.75V R2 PI6CB332000 85Ω R1 CK- SMA 42.5Ω 85Ω R2 50Ω Eq1. R1 + (R2 | | 50Ω) = 85Ω Eq2. ((42.5Ω | | 85Ω) + R1) | | R2 = 50Ω R1 = 47.8Ω, standard 1% value R1 = 47Ω R2 = 145.8Ω, standard 1% value R2 = 147Ω PI6CB332000 www.diodes.com July 2019 Document Number DS41283 Rev 4-2 10 Diodes Incorporated
PI6CB332000 HCSL Output DC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Condition Min. Typ. Max. Units
VOH Output Voltage High (1) 225 270 mV VOL Output Voltage Low (1) 10 0 150 mV VOMAX Output Voltage Maximum (Overshoot) (1) VOH + 75mV mV VOMIN Output Voltage Minimum (Undershoot) (1) VOL + 75mV mV Vcross absolute Absolute Crossing Point Voltage (1,2) 130 200 mV Vcross relative Relative Crossing Point Voltage (1,2) 35 mV DC Distor- tion Duty Cycle Distortion (3,4) -1 1 %
Note:
1. At default SMBUS amplitude settings. 2. Guaranteed by design and characterization—not 100% tested in production. 3. Measured from differential waveform. 4. Duty cycle distortion is the difference in duty cycle between the out and input clock when the device is operated in the PLL bypass mode.
HCSL Output DC Test Load
0.75V 85Ω R1 CK+ SMA 0.75V R2 PI6CB332000 85Ω R1 CK- SMA 42.5Ω 85Ω R2 50Ω Eq1. R1 + (R2 | | 50Ω) = 85Ω Eq2. ((42.5Ω | | 85Ω) + R1) | | R2 = 50Ω R1 = 47.8Ω, standard 1% value R1 = 47Ω R2 = 145.8Ω, standard 1% value R2 = 147Ω PI6CB332000 www.diodes.com July 2019 Document Number DS41283 Rev 4-2 10 Diodes Incorporated