Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 7

PRELIMINARY EZ-PD CCG6DF, CCG6SF Serial Communication Block (SCB)
connect to an I/O pin. Pin locations for fixed-function peripherals, such as USB Type-C ports, are also fixed to reduce internal CCG6DF and CCG6SF devices have four SCB blocks that can be configured for I2C, SPI, or UART. These blocks implement full multiplexing complexity. Data Output Registers and Pin State multi-master and slave I2C interfaces capable of multi-master Register store, respectively, the values to be driven on the pins and the states of the pins themselves. The configuration of the arbitration. I2C is compatible with the standard Philips I2C Speci- pins can be done by programming of registers through software fication V3.0. These blocks operate at speeds of up to 1 Mbps and have flexible buffering options to reduce interrupt overhead for each digital I/O Port. and latency for the CPU. Every I/O pin can generate an interrupt if so enabled and each The SCB blocks support 8-byte deep FIFOs for Receive and I/O port has an IRQ and ISR vector associated with it. Transmit, which, by increasing the time given for the CPU to read The I/O ports retain their state during Deep Sleep mode or data, greatly reduces the need for clock stretching caused by the remain ON. If operation is restored using reset, then the pins CPU not having read data on time. shall go the High-Z state. If operation is restored by an interrupt event, then the pin drivers shall retain their state until firmware
Timer, Counter, Pulse-Width Modulator (TCPWM)
chooses to change it. The I/Os (on data bus) do not draw current The TCPWM block of CCG6DF and CCG6SF supports up to two on power down. timers or counters or pulse-width modulators. These timers are All GPIOs reside in a separate I/O power domain – VDDIO to available for internal timer use by firmware or for providing provide flexible system-level interfacing. PWM-based functions on the GPIOs.
System Resources True Random Number Generator (TRNG)
Watchdog Timer (WDT) In notebook designs, CCG6DF’s and CCG6SF’s TRNG block is used in authenticating connected devices such as power A watchdog timer is implemented in the Clock block running from adapters or docks that include support for USB Type-C Authen- the internal low-speed oscillator (ILO) for CCG6DF and CCG6SF tication Specification (USBTCAS). CCG6DF and CCG6SF devices. This allows watchdog operation during Deep Sleep and devices, within notebook applications, are implemented as an generates a Watchdog Reset if not serviced before the timeout initiate role as defined in USBTCAS, while the connected device occurs. would implement the responder-role. USBTCAS provides a means for authenticating Type-C devices with regards to identi- Clock System fication and configuration. CCG6DF and CCG6SF have a fully integrated clock with no external crystal required. CCG6DF/CCG6SF clock system is
GPIO Interface
responsible for providing clocks to all subsystems that require The CCG6DF device has 23 GPIOs and the CCG6DSF device clocks (SCB and USB-PD) and for switching between different has 20 GPIOs including the I2C and SWD pins, which can also clock sources, without glitches. The clock system for these be used as GPIOs. devices consists of the internal main oscillator (IMO) and the ILO. The GPIO block implements the following: IMO Clock Source ■ Eight drive strength modes including strong push-pull, resistive The IMO is the primary source of internal clocking in CCG6DF pull-up and pull-down, weak (resistive) pull-up and pull-down, and CCG6SF devices with an accuracy of ±2%. The default IMO open drain and open source, input only, and disabled. frequency for CCG6DF and CCG6SF devices is 48 MHz ±2%. ■ Input threshold select (CMOS or LVTTL) ILO Clock Source ■ Individual control of input and output disables. The ILO is a very low power, relatively inaccurate, oscillator, which is primarily used to generate clocks for peripheral ■ Hold mode for latching previous state (used for retaining I/O operation in USB Suspend (Deep Sleep) mode. The typical state in Deep Sleep mode). frequency of the ILO is 32-kHz. ■ Selectable slew rates for dV/dt related noise control. During power-on and reset, the blocks are forced to the Disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may Document Number: 002-27161 Rev. *E Page 7 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support