Datasheet LTC6995-1, LTC6995-2 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | TimerBlox: Long Timer, Low Frequency Oscillator |
| 页数 / 页 | 28 / 9 — OPERATION. DIVCODE. Figure 1. Simple Technique for Setting DIVCODE |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
OPERATION. DIVCODE. Figure 1. Simple Technique for Setting DIVCODE
该数据表的模型线
- LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTC6995HS6-1#WTRMPBF LTC6995HS6-1#WTRPBF LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTC6995HS6-2#WTRMPBF LTC6995HS6-2#WTRPBF LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTC6995IS6-1#WTRMPBF LTC6995IS6-1#WTRPBF LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTC6995IS6-2#WTRMPBF LTC6995IS6-2#WTRPBF LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF
文件文字版本
link to page 9 link to page 10 link to page 10 link to page 10 link to page 10 LTC6995-1/LTC6995-2
OPERATION
The LTC6995 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled The DIV pin connects to an internal, V+ referenced 4-bit A/D by the SET pin current (ISET) and voltage (VSET), with a converter that determines the DIVCODE value. DIVCODE 1MHz • 50k conversion factor that is accurate to ±0.8% programs two settings on the LTC6995: under typical conditions. 1. DIVCODE determines the output frequency divider set- 1 I f SET ting, N MASTER = = 1MHz • 50kΩ • DIV . tMASTER VSET 2. DIVCODE determines the polarity of the RST and OUT A feedback loop maintains VSET at 1V ±30mV, leaving ISET pins, via the POL bit. as the primary means of controlling the output frequency. V The simplest way to generate I DIV may be generated by a resistor divider between V+ SET is to connect a resistor and GND as shown in Figure 1. (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: 2.25V TO 5.5V 1 1MHz • 50k V+ f Ω MASTER = = LTC6995 R1 tMASTER RSET DIV From this equation, it is clear that V R2 SET drift will not affect the output frequency when using a single program resistor GND (R 699512 F01 SET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ∆fOUT of the LTC6995.
Figure 1. Simple Technique for Setting DIVCODE
RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). Table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the Before reaching the OUT pin, the oscillator frequency corresponding NDIV and POL values for the recommended passes through a fixed ÷1024 divider. The LTC6995 also resistor pairs. Other values may be used as long as: includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 1. The VDIV/V+ ratio is accurate to ±1.5% (including resis- 218 or 221. The divider ratio N tor tolerances and temperature effects) DIV is set by a resistor divider attached to the DIV pin. 2. The driving impedance (R1||R2) does not exceed 500kΩ. 1MHz • 50k I If the voltage is generated by other means (i.e., the output f Ω SET OUT = • , or 1024 •N of a DAC) it must track the V+ supply voltage. The last DIV VSET column in Table 1 shows the ideal ratio of VDIV to the 1 N V supply voltage, which can also be calculated as: t DIV SET OUT = = • •1.024ms fOUT 50kΩ ISET VDIV DIVCODE + 0.5 = ± 1.5% with R V + 16 SET in place of VSET/ISET the equation reduces to: N For example, if the supply is 3.3V and the desired DIVCODE t DIV • RSET OUT = • 1.024ms is 4, V 50kΩ DIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. Rev. B 9 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
OPERATION
The LTC6995 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled The DIV pin connects to an internal, V+ referenced 4-bit A/D by the SET pin current (ISET) and voltage (VSET), with a converter that determines the DIVCODE value. DIVCODE 1MHz • 50k conversion factor that is accurate to ±0.8% programs two settings on the LTC6995: under typical conditions. 1. DIVCODE determines the output frequency divider set- 1 I f SET ting, N MASTER = = 1MHz • 50kΩ • DIV . tMASTER VSET 2. DIVCODE determines the polarity of the RST and OUT A feedback loop maintains VSET at 1V ±30mV, leaving ISET pins, via the POL bit. as the primary means of controlling the output frequency. V The simplest way to generate I DIV may be generated by a resistor divider between V+ SET is to connect a resistor and GND as shown in Figure 1. (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: 2.25V TO 5.5V 1 1MHz • 50k V+ f Ω MASTER = = LTC6995 R1 tMASTER RSET DIV From this equation, it is clear that V R2 SET drift will not affect the output frequency when using a single program resistor GND (R 699512 F01 SET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ∆fOUT of the LTC6995.
Figure 1. Simple Technique for Setting DIVCODE
RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). Table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the Before reaching the OUT pin, the oscillator frequency corresponding NDIV and POL values for the recommended passes through a fixed ÷1024 divider. The LTC6995 also resistor pairs. Other values may be used as long as: includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 1. The VDIV/V+ ratio is accurate to ±1.5% (including resis- 218 or 221. The divider ratio N tor tolerances and temperature effects) DIV is set by a resistor divider attached to the DIV pin. 2. The driving impedance (R1||R2) does not exceed 500kΩ. 1MHz • 50k I If the voltage is generated by other means (i.e., the output f Ω SET OUT = • , or 1024 •N of a DAC) it must track the V+ supply voltage. The last DIV VSET column in Table 1 shows the ideal ratio of VDIV to the 1 N V supply voltage, which can also be calculated as: t DIV SET OUT = = • •1.024ms fOUT 50kΩ ISET VDIV DIVCODE + 0.5 = ± 1.5% with R V + 16 SET in place of VSET/ISET the equation reduces to: N For example, if the supply is 3.3V and the desired DIVCODE t DIV • RSET OUT = • 1.024ms is 4, V 50kΩ DIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. Rev. B 9 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts