Datasheet LTC6991 (Analog Devices) - 9

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OPERATION
The LTC6991 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled The DIV pin connects to an internal, V+ referenced 4-bit by the SET pin current (ISET) and voltage (VSET), with a A/D converter that determines the DIVCODE value. 1MHz • 50k conversion factor that is accurate to ±0.8% DIVCODE programs two settings on the LTC6991: under typical conditions. 1. DIVCODE determines the output frequency divider set- 1 I f SET MASTER = = 1MHz • 50kΩ • ting, NDIV . tMASTER VSET 2. DIVCODE determines the polarity of the RST and OUT A feedback loop maintains VSET at 1V ±30mV, leaving ISET pins, via the POL bit. as the primary means of controlling the output frequency. V The simplest way to generate I DIV may be generated by a resistor divider between V+ SET is to connect a resistor and GND as shown in Figure 1. (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: 2.25V TO 5.5V 1 1MHz • 50k V+ f Ω MASTER = = LTC6991 R1 tMASTER RSET DIV From this equation, it is clear that V R2 SET drift will not affect the output frequency when using a single program resis- GND tor (R 6991 F01 SET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ∆fOUT of the LTC6991.
Figure 1. Simple Technique for Setting DIVCODE
RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). Table 1 offers recommended 1% resistor values that accu- rately produce the correct voltage division as well as the Before reaching the OUT pin, the oscillator frequency corresponding NDIV and POL values for the recommended passes through a fixed ÷1024 divider. The LTC6991 resistor pairs. Other values may be used as long as: also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 1. The VDIV/V+ ratio is accurate to ±1.5% (including resis- 215, 218 or 221. The divider ratio N tor tolerances and temperature effects) DIV is set by a resistor divider attached to the DIV pin. 2. The driving impedance (R1||R2) does not exceed 1MHz • 50k I 500kΩ. f Ω SET OUT = • , or 1024 • NDIV VSET If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last 1 N V t DIV SET column in Table 1 shows the ideal ratio of V OUT = = • • 1.024ms DIV to the fOUT 50kΩ ISET supply voltage, which can also be calculated as: with R V DIVCODE + 0.5 SET in place of VSET/ISET the equation reduces to: DIV = ± 1.5% V+ 16 N t DIV • RSET OUT = • 1.024ms 50kΩ For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. Rev. D For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts