Datasheet Si9407AEY (Vishay) - 2
| 制造商 | Vishay |
| 描述 | P-Channel 60-V (D-S), 175 °C MOSFET |
| 页数 / 页 | 5 / 2 — Si9407AEY. SPECIFICATIONS. Parameter Symbol. Test. Conditions. Min. … |
| 文件格式/大小 | PDF / 102 Kb |
| 文件语言 | 英语 |
Si9407AEY. SPECIFICATIONS. Parameter Symbol. Test. Conditions. Min. Typ.a. Max. Unit. Static. Dynamica
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Si9407AEY
Vishay Siliconix
SPECIFICATIONS
TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ.a Max. Unit Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = - 60 V, VGS = 0 V - 1 Zero Gate Voltage Drain Current IDSS µA VDS = - 60 V, VGS = 0 V, TJ = 55 °C - 10 On-State Drain Currentb I ≤ D(on) VDS - 5 V, VGS = - 10 V - 20 A VGS = - 10 V, ID = 3.5 A 0.120 Drain-Source On-State Resistanceb RDS(on) Ω VGS = - 4.5 V, ID = 3.1 A 0.150 Forward Transconductanceb gfs VDS = - 15 V, ID = - 3.5 A 8 S Diode Forward Voltageb VSD IS = - 2.5 A, VGS = 0 V - 1.2 V
Dynamica
Total Gate Charge Qg 18 30 Gate-Source Charge Q V gs DS = - 30 V, VGS = - 10 V, ID = - 3.5 A 5 nC Gate-Drain Charge Qgd 2 Turn-On Delay Time td(on) 8 15 Rise Time tr VDD = - 30 V, RL = 30 Ω 10 20 I Turn-Off Delay Time td(off) D ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 35 50 ns Fall Time tf 12 25 Source-Drain Reverse Recovery Time trr IF = - 2.5 A, dI/dt = 100 A/µs 70 100 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 70742 2 S09-1341-Rev. E, 13-Jul-09
Vishay Siliconix
SPECIFICATIONS
TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ.a Max. Unit Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = - 60 V, VGS = 0 V - 1 Zero Gate Voltage Drain Current IDSS µA VDS = - 60 V, VGS = 0 V, TJ = 55 °C - 10 On-State Drain Currentb I ≤ D(on) VDS - 5 V, VGS = - 10 V - 20 A VGS = - 10 V, ID = 3.5 A 0.120 Drain-Source On-State Resistanceb RDS(on) Ω VGS = - 4.5 V, ID = 3.1 A 0.150 Forward Transconductanceb gfs VDS = - 15 V, ID = - 3.5 A 8 S Diode Forward Voltageb VSD IS = - 2.5 A, VGS = 0 V - 1.2 V
Dynamica
Total Gate Charge Qg 18 30 Gate-Source Charge Q V gs DS = - 30 V, VGS = - 10 V, ID = - 3.5 A 5 nC Gate-Drain Charge Qgd 2 Turn-On Delay Time td(on) 8 15 Rise Time tr VDD = - 30 V, RL = 30 Ω 10 20 I Turn-Off Delay Time td(off) D ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 35 50 ns Fall Time tf 12 25 Source-Drain Reverse Recovery Time trr IF = - 2.5 A, dI/dt = 100 A/µs 70 100 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 70742 2 S09-1341-Rev. E, 13-Jul-09