Datasheet ADAR1000 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer |
| 页数 / 页 | 65 / 3 — Data Sheet. ADAR1000. SPECIFICATIONS. Table 1. Parameter. Test … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
Data Sheet. ADAR1000. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADAR1000 SPECIFICATIONS
AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, and the device is programmed to the maximum channel gain and the nominal bias conditions, unless otherwise noted. Nominal bias register settings: Register 0x034 = 0x08, Register 0x035 = 0x55, Register 0x036 = 0x2D, and Register 0x37 = 0x06. Low power bias register settings: Register 0x034 = 0x05, Register 0x035 = 0x1A, Register 0x036 = 0x2A, and Register 0x37 = 0x03.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OPERATING CONDITIONS RF Range 8 16 GHz Operating Temperature −40 +85 °C TRANSMIT SECTION RF_IO, TX1, TX2, TX3, and TX4 pins Maximum Gain 9.5 GHz 21 dB 11.5 GHz 19 dB 14 GHz 16 dB Gain Flatness vs. Frequency Across any 1 GHz bandwidth dB From 9 GHz to 14 GHz ±1.0 dB From 8 GHz to 15 GHz ±1.7 dB Gain Variation vs. Temperature 11.5 GHz ±2.5 dB Output 1 dB Compression (P1dB) Maximum gain setting Nominal Bias Setting 9.5 GHz 10 dBm 11.5 GHz 10 dBm 14 GHz 10 dBm Low Bias Setting 9.5 GHz 6 dBm 11.5 GHz 8 dBm 14 GHz 7 dBm Saturated Power (PSAT) Maximum gain setting Nominal Bias Setting 9.5 GHz 14 dBm 11.5 GHz 14 dBm 14 GHz 13 dBm Low Bias Setting 9.5 GHz 14 dBm 11.5 GHz 14 dBm 14 GHz 13 dBm Gain Resolution ≤0.5 dB Root Mean Square (RMS) Gain Error Over phase settings and frequencies 0.2 dB Phase Adjustment Range 360 Degrees Phase Resolution 2.8 Degrees RMS Phase Error Over phase settings and frequencies 2 Degrees Noise Figure Maximum gain setting Nominal Bias Setting 9.5 GHz 22 dB 11.5 GHz 23 dB 14 GHz 25 dB Low Bias Setting 9.5 GHz 22 dB 11.5 GHz 23 dB 14 GHz 25 dB Channel to Channel Isolation1 −40 dB Transmit Output to RF_IO Maximum gain setting, 9.5 GHz −60 dB Rev. A | Page 3 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide
Data Sheet ADAR1000 SPECIFICATIONS
AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, and the device is programmed to the maximum channel gain and the nominal bias conditions, unless otherwise noted. Nominal bias register settings: Register 0x034 = 0x08, Register 0x035 = 0x55, Register 0x036 = 0x2D, and Register 0x37 = 0x06. Low power bias register settings: Register 0x034 = 0x05, Register 0x035 = 0x1A, Register 0x036 = 0x2A, and Register 0x37 = 0x03.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OPERATING CONDITIONS RF Range 8 16 GHz Operating Temperature −40 +85 °C TRANSMIT SECTION RF_IO, TX1, TX2, TX3, and TX4 pins Maximum Gain 9.5 GHz 21 dB 11.5 GHz 19 dB 14 GHz 16 dB Gain Flatness vs. Frequency Across any 1 GHz bandwidth dB From 9 GHz to 14 GHz ±1.0 dB From 8 GHz to 15 GHz ±1.7 dB Gain Variation vs. Temperature 11.5 GHz ±2.5 dB Output 1 dB Compression (P1dB) Maximum gain setting Nominal Bias Setting 9.5 GHz 10 dBm 11.5 GHz 10 dBm 14 GHz 10 dBm Low Bias Setting 9.5 GHz 6 dBm 11.5 GHz 8 dBm 14 GHz 7 dBm Saturated Power (PSAT) Maximum gain setting Nominal Bias Setting 9.5 GHz 14 dBm 11.5 GHz 14 dBm 14 GHz 13 dBm Low Bias Setting 9.5 GHz 14 dBm 11.5 GHz 14 dBm 14 GHz 13 dBm Gain Resolution ≤0.5 dB Root Mean Square (RMS) Gain Error Over phase settings and frequencies 0.2 dB Phase Adjustment Range 360 Degrees Phase Resolution 2.8 Degrees RMS Phase Error Over phase settings and frequencies 2 Degrees Noise Figure Maximum gain setting Nominal Bias Setting 9.5 GHz 22 dB 11.5 GHz 23 dB 14 GHz 25 dB Low Bias Setting 9.5 GHz 22 dB 11.5 GHz 23 dB 14 GHz 25 dB Channel to Channel Isolation1 −40 dB Transmit Output to RF_IO Maximum gain setting, 9.5 GHz −60 dB Rev. A | Page 3 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide