Datasheet KSZ8862-16M, KSZ8862-32M (Microchip) - 5

KSZ8862-16M/-32M 1.0 INTRODUCTION 1.1 General Description
The KSZ8862M is two-port switch with non-PCI CPU interface and fiber support, and is available in 8-/16-bit and 32-bit bus designs. This data sheet describes the KSZ8862M non-PCI CPU interface chip. The KSZ8862M is the industry’s first fully managed, two-port switch with a non-PCI CPU interface and fiber support. It is based on a proven, fourth generation, integrated two layer switch, compliant with IEEE 802.3u standards. For industrial applications, the KSZ8862M can run in half-duplex mode regardless of the application. In fiber mode, port one can be configurable to either 100BASE-FX or 100BASE-SX/10BASE-FL. The LED driver and post amplifier are also included for 10Base-FL and 100Base-SX applications. In copper mode, port two supports 10/100BASE-T/TX with HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. Microchip’s proprietary LinkMD® Time Domain Reflectometry (TDR)-based function is also available for determining the cable length, as well as cable diagnostics for identifying faulty cabling. The KSZ8862M offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority man- agement, management information base (MIB) counters, and CPU control/data interfaces to effectively address Fast Ethernet applications. The KSZ8862M contains: Two 10/100 transceivers with patented, mixed-signal, low-power technology, two media access control (MAC) units, a direct memory access (DMA) channel, a high-speed, non-blocking, switch fabric, a ded- icated 1K entry forwarding table, and an on-chip frame buffer memory.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM TX 1K look-up LED 10/100 Base- Engine Port 1 Driver 10/100 FL/FX/SX Fiber MAC 1 Post PHY 1 Amp RX
FIF
Scheduling
O
10/100 Base- Port 2 10/100
, Flow Control, V
Management T/TX Copper MAC 2 PHY 2 Buffer Management RXQ QMU Switch
L
4KB
AN
DMA Host Non-PCI Channel TXQ MAC
Ta
CPU Embedded 4KB
gging
Bus Processor Interface Frame Interface Buffers Unit
,Priority
Control Registers 8,16, or 32-bit Generic Host MIB Interface Counters P1 LED[3:0] LED EEPROM Drivers Interface P2 LED[3:0] EEPROM I/F
 2020 Microchip Technology Inc. DS00003324A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service