Datasheet KSZ8893FQL (Microchip)
| 制造商 | Microchip |
| 描述 | Single-Chip 3-Port Switch with Fiber Support |
| 页数 / 页 | 109 / 1 — KSZ8893FQL. Single-Chip 3-Port Switch with Fiber Support. Features. • … |
| 文件格式/大小 | PDF / 2.2 Mb |
| 文件语言 | 英语 |
KSZ8893FQL. Single-Chip 3-Port Switch with Fiber Support. Features. • Integrated 3-Port 10/100 Ethernet Switch
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KSZ8893FQL Single-Chip 3-Port Switch with Fiber Support Features
- Control Registers Configurable on the Fly (Port-
• Integrated 3-Port 10/100 Ethernet Switch
Priority, 802.1p/d/q, AN…) - Three MACs and Two PHYs Fully Compliant
• QoS/CoS Packet Prioritization Support
with IEEE 802.3u Standard - Per Port, 802.1p, and DiffServ-Based - Non-Blocking Switch Fabric Ensures Fast - Re-Mapping of 802.1p Priority Field Per Port Packet Delivery by Utilizing an 1K MAC Basis Address Lookup Table and a Store-and-Forward - Four Priority Levels Architecture
• Advanced Switch Features
- Full-Duplex IEEE 802.3x Flow Control (PAUSE) - IEEE 802.1q VLAN Support for Up to 16 Groups with Force Mode Option (Full Range of VLAN IDs) - Half-Duplex Back Pressure Flow Control - VLAN ID Tag/Untag Options, Per Port Basis - HP Auto MDI-X for Reliable Detection of and - IEEE 802.1p/q Tag Insertion or Removal on a Correction for Straight-Through and Crossover Per Port Basis (Egress) Cables with Disable and Enable Option - Programmable Rate Limiting at the Ingress and - Microchip LINKMD® TDR-Based Cable Diag- Egress on a Per Port Basis nostics Permit Identification of Faulty Copper - Broadcast Storm Protection with Percent Con- Cabling trol (Global and Per Port Basis) - 100BASE-FX, 100BASE-SX, and 10BASE-FL - IEEE 802.1d Spanning Tree Protocol Support Fiber Support on Port 1 - Special Tagging Mode to Inform the Processor - MII Interface Supports Both MAC Mode and which Ingress Port Receives the Packet PHY Mode - IGMP Snooping (IPv4) and MLD Snooping - RMII Interface Support with External 50 MHz (IPv6) Support for Multicast Packet Filtering System Clock - MAC Filtering Function to Forward Unknown - 7-Wire Serial Network Interface (SNI) Support Unicast Packets to Specified Port for Legacy MAC - Double-Tagging Support - Comprehensive LED Indicator Support for Link,
• Low Latency Support
Activity, Full-/Half-Duplex and 10/100 Speed - Repeater Mode
• Fiber Support • Switch Monitoring Features
- Integrated LED Driver and Post Amplifier for - Port Mirroring/Monitoring/Sniffing: Ingress and/ 10BASE-FL and 100BASE-SX Optical Modules or Egress Traffic to Any Port or MII
• TTC TS-1000 OAM
- MIB Counters for Fully Compliant Statistics - Supports OAM Sub-Layer which Conforms to Gathering, 34 MIB Counters Per Port TS-1000 V2 Specification from Telecommunica- - Loopback Modes for Remote Diagnostic of Fail- tion Technology Committee (TTC) ure - Sends and Receives OAM Frames to Center or
• Low Power Dissipation
Terminal Side - Full-Chip Hardware Power-Down (Register - Loopback Mode to Support Loopback Packet Configuration Not Saved) from Center Side to Terminal Side - Per Port Based Software Power-Save on PHY - Far-End Fault Detection with Disable and (Idle Link Detection, Register Configuration Pre- Enable served) - Link Transparency to Indicate Link Down from - Voltages: Core 1.2V, I/O and Transceiver 3.3V Link Partner
• Available in a 128-Pin PQFP, Lead-Free Package
- Unique User Defined Register (UDR) Feature Brings OAM to Low Cost/Complexity Nodes
Applications • Comprehensive Configuration Register Access
• Media Conversion Modules - SMI, SPI, and I2C Management Interfaces to All - 10BASE-FL to/from 10BASE-T 8-bit Internal Registers - 100BASE-SX to/from 100BASE-TX - MII Management (MIIM) Interface to PHY Reg- - 100BASE-FX to/from 100BASE-TX isters • FTTx Managed/Unmanaged Media Converters - I/O Pins Strapping and EEPROM to Program • Fiber Broadband Gateways Selective Registers in Unmanaged Switch Mode 2019 Microchip Technology Inc. DS00003038B-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
- Control Registers Configurable on the Fly (Port-
• Integrated 3-Port 10/100 Ethernet Switch
Priority, 802.1p/d/q, AN…) - Three MACs and Two PHYs Fully Compliant
• QoS/CoS Packet Prioritization Support
with IEEE 802.3u Standard - Per Port, 802.1p, and DiffServ-Based - Non-Blocking Switch Fabric Ensures Fast - Re-Mapping of 802.1p Priority Field Per Port Packet Delivery by Utilizing an 1K MAC Basis Address Lookup Table and a Store-and-Forward - Four Priority Levels Architecture
• Advanced Switch Features
- Full-Duplex IEEE 802.3x Flow Control (PAUSE) - IEEE 802.1q VLAN Support for Up to 16 Groups with Force Mode Option (Full Range of VLAN IDs) - Half-Duplex Back Pressure Flow Control - VLAN ID Tag/Untag Options, Per Port Basis - HP Auto MDI-X for Reliable Detection of and - IEEE 802.1p/q Tag Insertion or Removal on a Correction for Straight-Through and Crossover Per Port Basis (Egress) Cables with Disable and Enable Option - Programmable Rate Limiting at the Ingress and - Microchip LINKMD® TDR-Based Cable Diag- Egress on a Per Port Basis nostics Permit Identification of Faulty Copper - Broadcast Storm Protection with Percent Con- Cabling trol (Global and Per Port Basis) - 100BASE-FX, 100BASE-SX, and 10BASE-FL - IEEE 802.1d Spanning Tree Protocol Support Fiber Support on Port 1 - Special Tagging Mode to Inform the Processor - MII Interface Supports Both MAC Mode and which Ingress Port Receives the Packet PHY Mode - IGMP Snooping (IPv4) and MLD Snooping - RMII Interface Support with External 50 MHz (IPv6) Support for Multicast Packet Filtering System Clock - MAC Filtering Function to Forward Unknown - 7-Wire Serial Network Interface (SNI) Support Unicast Packets to Specified Port for Legacy MAC - Double-Tagging Support - Comprehensive LED Indicator Support for Link,
• Low Latency Support
Activity, Full-/Half-Duplex and 10/100 Speed - Repeater Mode
• Fiber Support • Switch Monitoring Features
- Integrated LED Driver and Post Amplifier for - Port Mirroring/Monitoring/Sniffing: Ingress and/ 10BASE-FL and 100BASE-SX Optical Modules or Egress Traffic to Any Port or MII
• TTC TS-1000 OAM
- MIB Counters for Fully Compliant Statistics - Supports OAM Sub-Layer which Conforms to Gathering, 34 MIB Counters Per Port TS-1000 V2 Specification from Telecommunica- - Loopback Modes for Remote Diagnostic of Fail- tion Technology Committee (TTC) ure - Sends and Receives OAM Frames to Center or
• Low Power Dissipation
Terminal Side - Full-Chip Hardware Power-Down (Register - Loopback Mode to Support Loopback Packet Configuration Not Saved) from Center Side to Terminal Side - Per Port Based Software Power-Save on PHY - Far-End Fault Detection with Disable and (Idle Link Detection, Register Configuration Pre- Enable served) - Link Transparency to Indicate Link Down from - Voltages: Core 1.2V, I/O and Transceiver 3.3V Link Partner
• Available in a 128-Pin PQFP, Lead-Free Package
- Unique User Defined Register (UDR) Feature Brings OAM to Low Cost/Complexity Nodes
Applications • Comprehensive Configuration Register Access
• Media Conversion Modules - SMI, SPI, and I2C Management Interfaces to All - 10BASE-FL to/from 10BASE-T 8-bit Internal Registers - 100BASE-SX to/from 100BASE-TX - MII Management (MIIM) Interface to PHY Reg- - 100BASE-FX to/from 100BASE-TX isters • FTTx Managed/Unmanaged Media Converters - I/O Pins Strapping and EEPROM to Program • Fiber Broadband Gateways Selective Registers in Unmanaged Switch Mode 2019 Microchip Technology Inc. DS00003038B-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service