Datasheet KSZ8893FQL (Microchip) - 4
| 制造商 | Microchip |
| 描述 | Single-Chip 3-Port Switch with Fiber Support |
| 页数 / 页 | 109 / 4 — KSZ8893FQL. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. … |
| 文件格式/大小 | PDF / 2.2 Mb |
| 文件语言 | 英语 |
KSZ8893FQL. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. SYSTEM BLOCK DIAGRAM
该数据表的模型线
文件文字版本
KSZ8893FQL 1.0 INTRODUCTION 1.1 General Description
The KSZ8893FQL, a highly integrated single-chip 3-port Fast Ethernet switch is designed for applications with fiber sup- port such as media converter. It provides two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a Layer-2 managed switch and TS- 1000 OAM (Operations, Administration and Management) V2 in a compact solution. Backwards compatible to the TS- 1000 (2002) specification, TS-1000 V2 is an OAM sub-layer that provides communication between CO (central office) and CPE (customer premises equipment). In fiber mode, one PHY unit can be configurable to 100BASE-FX, 100BASE-SX, or 10BASE-FL fiber for conversion to 10BASE-T and 100BASE-TX copper. A fiber LED driver and post amplifier are also included for 10BASE-FL and 100BASE-SX applications. In copper mode, both PHY units support 10BASE-T and 100BASE-TX with HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables, and LINKMD® TDR-based cable diagnostics for identification of faulty cabling. The high-performance switching engine features an extensive feature set that includes programmable rate limiting, tag/ port-based VLAN, 4 priority class, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KSZ8893FQL comes in a lead-free package.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
TO CONTROL REGISTERS 1K LOOK-UP FIFO, FLOW CONTROL, VL ENGINE 10/100 O HP AUTO 10/100 FL/FX/SX A MDIX MAC 1 PHY 1 M QUEUE MANAGEMENT 10/100 HP AUTO 10/100 T/TX MDIX MAC 2 PHY 2 BUFFER MANAGEMENT RMII/MII/ 10/100 AN TAGGI SNI MAC 3 FRAME BUFFERS SNI N G, PRIOR MIB SPI SPI COUNTERS ITY MIIM CONTROL EEPROM REGISTERS INTERFACE SMI I2C P1 LED[3:0] LED STRAP IN DRIVERS CONFIGURATION P2 LED[3:0] DS00003038B-page 4 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
The KSZ8893FQL, a highly integrated single-chip 3-port Fast Ethernet switch is designed for applications with fiber sup- port such as media converter. It provides two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a Layer-2 managed switch and TS- 1000 OAM (Operations, Administration and Management) V2 in a compact solution. Backwards compatible to the TS- 1000 (2002) specification, TS-1000 V2 is an OAM sub-layer that provides communication between CO (central office) and CPE (customer premises equipment). In fiber mode, one PHY unit can be configurable to 100BASE-FX, 100BASE-SX, or 10BASE-FL fiber for conversion to 10BASE-T and 100BASE-TX copper. A fiber LED driver and post amplifier are also included for 10BASE-FL and 100BASE-SX applications. In copper mode, both PHY units support 10BASE-T and 100BASE-TX with HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables, and LINKMD® TDR-based cable diagnostics for identification of faulty cabling. The high-performance switching engine features an extensive feature set that includes programmable rate limiting, tag/ port-based VLAN, 4 priority class, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KSZ8893FQL comes in a lead-free package.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
TO CONTROL REGISTERS 1K LOOK-UP FIFO, FLOW CONTROL, VL ENGINE 10/100 O HP AUTO 10/100 FL/FX/SX A MDIX MAC 1 PHY 1 M QUEUE MANAGEMENT 10/100 HP AUTO 10/100 T/TX MDIX MAC 2 PHY 2 BUFFER MANAGEMENT RMII/MII/ 10/100 AN TAGGI SNI MAC 3 FRAME BUFFERS SNI N G, PRIOR MIB SPI SPI COUNTERS ITY MIIM CONTROL EEPROM REGISTERS INTERFACE SMI I2C P1 LED[3:0] LED STRAP IN DRIVERS CONFIGURATION P2 LED[3:0] DS00003038B-page 4 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service