Datasheet ADP1074 (Analog Devices) - 4

ADP1074 Data Sheet SPECIFICATIONS
VIN = 24 V, VDD2 = 12 V, TJ = −40°C to +125°C, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY (PRIMARY) Supply Voltage VIN 4.7 µF capacitor from VIN to PGND1, 4.7 24 60 V 1 µF capacitor from VREG1 to PGND1 Quiescent Supply Current IVIN VIN > VIN UVLO, NGATE and PGATE unloaded At 100 kHz 5.3 mA At 300 kHz 5.8 mA At 600 kHz 6.8 mA VIN > VIN UVLO, NGATE and PGATE loaded with 2.2 nF and 410 pF, respectively At 100 kHz 7.5 mA At 300 kHz 12 mA At 600 kHz 19.5 mA VIN Shutdown Current EN pin voltage (VEN) < 1.2 V, VREG1 = 0 V, 55 μA VIN = 60 V (VIN + VREG1) Start-Up Current IVIN_STARTUP VEN < 1.2 V, VREG1 = 12 V, VIN = 12 V 160 μA VIN UVLO VIN rising 4.7 V VIN falling 4.0 V UVLO Hysteresis 0.19 V Time from EN High to PGATE VEN > 1.2 V, 1 µF capacitor on VREG1 1 ms Output Switching Time from EN Low to SR1/SR2 VEN < 1.0 V, 1 µF capacitor on VREG1 1 μs Output Stops Switching SUPPLY (SECONDARY) Supply Voltage VDD2 4.7 µF capacitor from VDD2 to PGND2, 4.5 12 36 V 1 µF capacitor from VREG2 to PGND2 Quiescent Supply Current IDD2 SR1 and SR2 unloaded At 100 kHz 6.5 mA At 300 kHz 6.7 mA At 600 kHz 7 mA IDD2 SR1 and SR2 loaded with 2.2 nF At 100 kHz 8.3 mA At 300 kHz 12 mA At 600 kHz 18 mA VDD2 UVLO Threshold VDD2 rising 3.55 V VDD2 falling 3.0 V UVLO Hysteresis 0.145 V Secondary UVLO Hiccup Time 200 ms OSCILLATOR Switching Frequency (fS) RT resistance (RRT) = 480 kΩ (±1%) 50 − 10% 50 50 + 10% kHz RRT = 240 kΩ (±1%) 100 − 10% 100 100 + 10% kHz RRT = 120 kΩ (±1%) 200 − 10% 200 200 + 10% kHz RRT = 80 kΩ (±1%) 300 − 10% 300 300 + 10% kHz RRT = 60 kΩ (±1%) 400 − 10% 400 400 + 10% kHz RRT = 40 kΩ (±1%) 600 − 10% 600 600 + 10% kHz VREG1 PIN VREG1 Voltage Clamp VREG1 current (IVREG1) = 3 mA, VEN < 1.2 V 13.5 14.3 15.2 V VREG1 Clamp Series Resistance VREG1 forced current of 5 mA and 15 mA 16 Ω Rev. C | Page 4 of 32 Document Outline FEATURES APPLICATIONS SIMPLIFIED BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS INSULATION AND SAFETY RELATED SPECIFICATIONS REGULATORY INFORMATION DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION DETAILED BLOCK DIAGRAM PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO SECONDARY SIDE SUPPLY AND LDO PRECISION ENABLE SOFT START PROCEDURE OUTPUT VOLTAGE SENSING AND FEEDBACK LOOP COMPENSATION AND STEADY STATE OPERATION SLOPE COMPENSATION INPUT/OUTPUT CURRENT-LIMIT PROTECTION TEMPERATURE SENSING FREQUENCY SETTING (RT PIN) MAXIMUM DUTY CYCLE FREQUENCY SYNCHRONIZATION SYNCHRONOUS RECTIFIER (SR) DRIVERS OUTPUT OVERVOLTAGE PROTECTION (OVP) ACTIVE CLAMP (PGATE) LEADING EDGE BLANKING GATE DELAY AND SR DEAD TIME LIGHT LOAD MODE (LLM) AND SR PHASE IN EXTERNAL START-UP CIRCUIT SOFT STOP POWER GOOD OCP/FEEDBACK RECOVERY OUTPUT VOLTAGE TRACKING REMOTE SYSTEM RESET OCP COUNTER INSULATION LIFETIME LAYOUT GUIDELINES TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES