Datasheet ADP1074 (Analog Devices) - 5

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Data Sheet ADP1074 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GATE DRIVERS (PRIMARY) NGATE and PGATE High IVREG1 = 20 mA, VIN > 9 V 7.8 8 8.2 V Voltage Gate Short-Circuit Peak 8 V on VREG1 1.0 A Current1 Rise Time 10% to 90% NGATE CNGATE = 2.2 nF 18 ns PGATE CPGATE = 410 pF 8 ns Fall Time 90% to 10% NGATE CNGATE = 2.2 nF 16 ns PGATE CPGATE = 410 pF 7 ns Source Resistance RON_SOURCE Source 100 mA NGATE 4 Ω PGATE 6.5 Ω Sink Resistance RON_SINK Sink 100 mA NGATE 3 Ω PGATE 3.5 Ω NGATE Maximum Duty Cycle DMAX Divider bottom resistor (RBOT) = 0 Ω 45 50 55 % Divider top resistor (RTOP) = RBOT, 75 % 1% resistors NGATE Minimum On Time Includes propagation delay and CS 170 ns comparator blanking time SRx DRIVERS (SECONDARY) SR1 and SR2 High Voltage IVREG2 = 15 mA, VDD2 > 5.5 V 4.9 5 5.1 V Gate Short-Circuit Peak 5 V on VREG2 1.0 A Current1 SRx Time CSRx = 2.2 nF Rise 10% to 90% 14 ns Fall 90% to 10% 11 ns Minimum On Includes blanking time 230 ns SRx Resistance Source RON_SR_SOURCE Source 100 mA 3.5 Ω Sink RON_SR_SINK Sink 100 mA 2 Ω DELAYS Gate Delay (SR1 Rising to 35 ns NGATE Rising) Delay Between NGATE Falling iCoupler 21 ns Edge and SR1 Falling Edge delay SR DEAD TIME (PGATE RISING Resistor (±5%) at NGATE TO SR2 FALLING) Dead time resistor (RDT) = 10 kΩ 154 ns RDT = 22 kΩ 109 ns RDT = 47 kΩ 72 ns RDT is open 42 ns SR1 and SR2 Dead Time Dead time between SR1 and SR2 25 ns CURRENT-LIMIT SENSE (PRIMARY) CS Limit Threshold VCS_LIM Over current sense limit threshold 120 mV CS Leading Edge Blanking Time 150 ns Current Source di/dt for Slope Switching period (tS) = 1/fS 20 μA per tS Compensation Rev. C | Page 5 of 32 Document Outline FEATURES APPLICATIONS SIMPLIFIED BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS INSULATION AND SAFETY RELATED SPECIFICATIONS REGULATORY INFORMATION DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION DETAILED BLOCK DIAGRAM PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO SECONDARY SIDE SUPPLY AND LDO PRECISION ENABLE SOFT START PROCEDURE OUTPUT VOLTAGE SENSING AND FEEDBACK LOOP COMPENSATION AND STEADY STATE OPERATION SLOPE COMPENSATION INPUT/OUTPUT CURRENT-LIMIT PROTECTION TEMPERATURE SENSING FREQUENCY SETTING (RT PIN) MAXIMUM DUTY CYCLE FREQUENCY SYNCHRONIZATION SYNCHRONOUS RECTIFIER (SR) DRIVERS OUTPUT OVERVOLTAGE PROTECTION (OVP) ACTIVE CLAMP (PGATE) LEADING EDGE BLANKING GATE DELAY AND SR DEAD TIME LIGHT LOAD MODE (LLM) AND SR PHASE IN EXTERNAL START-UP CIRCUIT SOFT STOP POWER GOOD OCP/FEEDBACK RECOVERY OUTPUT VOLTAGE TRACKING REMOTE SYSTEM RESET OCP COUNTER INSULATION LIFETIME LAYOUT GUIDELINES TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES