Datasheet AD5593R (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, I2C Interface |
| 页数 / 页 | 33 / 6 — AD5593R. Data Sheet. TIMING CHARACTERISTICS. Table 3. Parameter1. Min. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 802 Kb |
| 文件语言 | 英语 |
AD5593R. Data Sheet. TIMING CHARACTERISTICS. Table 3. Parameter1. Min. Typ. Max. Unit. Conditions/Comments. Timing Diagram. SDA. SCL. START
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文件文字版本
AD5593R Data Sheet TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1 Min Typ Max Unit Conditions/Comments
t1 2.5 µs SCL cycle time t2 0.6 µs tHIGH, SCL high time t3 1.3 µs tLOW, SCL low time t4 0.6 µs tHD,STA, start/repeated start condition hold time t5 100 ns tSU,DAT, data setup time t 2 6 0.9 µs tHD,DAT, data hold time t7 0.6 µs tSU,STA, setup time for repeated start t8 0.6 µs tSU,STO, stop condition setup time t9 1.3 µs tBUF, bus free time between a stop and a start condition t10 300 ns tR, rise time of SCL and SDA when receiving 0 ns tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 250 ns tF, fall time of SDA when transmitting 0 ns tF, fall time of SDA when receiving (CMOS compatible) 300 ns tF, fall time of SCL and SDA when receiving 20 + 0.1C 3 B ns tF, fall time of SCL and SDA when transmitting C 3 B 400 pF Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram SDA t t 9 t3 11 t t 4 10 SCL t2 t t 4 t6 5 t7 t1 t8 START REPEATED STOP
002
CONDITION START CONDITION CONDITION
12507- Figure 2. 2-Wire Serial Interface Timing Diagram Rev. D | Page 6 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1 Min Typ Max Unit Conditions/Comments
t1 2.5 µs SCL cycle time t2 0.6 µs tHIGH, SCL high time t3 1.3 µs tLOW, SCL low time t4 0.6 µs tHD,STA, start/repeated start condition hold time t5 100 ns tSU,DAT, data setup time t 2 6 0.9 µs tHD,DAT, data hold time t7 0.6 µs tSU,STA, setup time for repeated start t8 0.6 µs tSU,STO, stop condition setup time t9 1.3 µs tBUF, bus free time between a stop and a start condition t10 300 ns tR, rise time of SCL and SDA when receiving 0 ns tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 250 ns tF, fall time of SDA when transmitting 0 ns tF, fall time of SDA when receiving (CMOS compatible) 300 ns tF, fall time of SCL and SDA when receiving 20 + 0.1C 3 B ns tF, fall time of SCL and SDA when transmitting C 3 B 400 pF Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram SDA t t 9 t3 11 t t 4 10 SCL t2 t t 4 t6 5 t7 t1 t8 START REPEATED STOP
002
CONDITION START CONDITION CONDITION
12507- Figure 2. 2-Wire Serial Interface Timing Diagram Rev. D | Page 6 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide