Datasheet AD5593R (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, I2C Interface |
| 页数 / 页 | 33 / 9 — Data Sheet. AD5593R. ESET. VDD 1. 12 GND. I/O0 2. 11 I/O7. I/O1. TOP … |
| 修订版 | D |
| 文件格式/大小 | PDF / 802 Kb |
| 文件语言 | 英语 |
Data Sheet. AD5593R. ESET. VDD 1. 12 GND. I/O0 2. 11 I/O7. I/O1. TOP VIEW. 10 I/O6. (Not to Scale). I/O2 4. I/O5. I/O3. REV. OGIC. I/O4
该数据表的模型线
文件文字版本
Data Sheet AD5593R ESET CL DA A0 R S S 16 15 14 13 VDD 1 12 GND I/O0 2 AD5593R 11 I/O7 I/O1 TOP VIEW 3 10 I/O6 (Not to Scale) I/O2 4 9 I/O5 5 6 7 8 F
004
I/O3 REV OGIC I/O4 LV
12507- Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. 16-Ball LFCSP Pin Function Descriptions Pin No. Mnemonic Description
1 VDD Power Supply Input. The AD5593R operates from 2.7 V to 5.5 V. Decouple the supply with a 0.1 µF capacitor to GND. 2 to 5, 8 to 11 I/O0 to I/O7 Input/Output 0 through Input/Output 7. These pins can be independently configured as DACs, ADCs, or general- purpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in the configuration registers. 6 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. 7 VLOGIC Interface Power Supply. The voltage ranges from 1.8 V to 5.5 V. 12 GND Ground Reference Point for All Circuitry. 13 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the input shift register. SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor. 14 SCL Serial Clock Line. This is pin used in conjunction with the SDA line to clock data into or out of the 16-bit input register. 15 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset to its default configuration. 16 A0 Address Input. This pin sets the LSB of the 7-bit slave address. Rev. D | Page 9 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide
004
I/O3 REV OGIC I/O4 LV
12507- Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. 16-Ball LFCSP Pin Function Descriptions Pin No. Mnemonic Description
1 VDD Power Supply Input. The AD5593R operates from 2.7 V to 5.5 V. Decouple the supply with a 0.1 µF capacitor to GND. 2 to 5, 8 to 11 I/O0 to I/O7 Input/Output 0 through Input/Output 7. These pins can be independently configured as DACs, ADCs, or general- purpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in the configuration registers. 6 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. 7 VLOGIC Interface Power Supply. The voltage ranges from 1.8 V to 5.5 V. 12 GND Ground Reference Point for All Circuitry. 13 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the input shift register. SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor. 14 SCL Serial Clock Line. This is pin used in conjunction with the SDA line to clock data into or out of the 16-bit input register. 15 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset to its default configuration. 16 A0 Address Input. This pin sets the LSB of the 7-bit slave address. Rev. D | Page 9 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide