Datasheet AD5592R (Analog Devices) - 7

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Data Sheet AD5592R Parameter Min Typ Max Unit1 Test Conditions/Comments
VDD = 3 V (Normal Mode) 1.1 mA I/O0 to I/O7 are DACs, internal reference, gain = 1 1 mA I/O0 to I/O7 are DACs, external reference, gain = 1 1.1 mA I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 1 0.78 mA I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 1 0.75 mA I/O0 to I/O7 are ADCs, internal reference, gain = 1 0.5 mA I/O0 to I/O7 are ADCs, external reference, gain = 1 0.45 mA I/O0 to I/O7 are general-purpose outputs 0.45 mA I/O0 to I/O7 are general-purpose inputs VLOGIC 1.62 VDD V AD5592R-1 only ILOGIC 3 µA AD5592R-1 only 1 All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below ful scale, unless otherwise noted. 2 Guaranteed by design and characterization; not production tested. 3 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of 10 mV when VREF = VDD. 4 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33).
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested; all input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted.
Table 3. AD5592R T iming Characteristics Parameter 2.7 V ≤ VDD < 3 V 3 V ≤ VDD ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation 50 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC falling edge to SCLK falling edge setup time 2 2 µs max SYNC falling edge to SCLK falling edge setup time1 t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for register write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 25 25 ns max SCLK rising edge to SDO valid t11 250 250 ns min RESET low pulse width (not shown in Figure 4) 1 When reading an ADC conversion. Rev. E | Page 7 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide