Datasheet AD7294-2 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense |
| 页数 / 页 | 44 / 4 — AD7294-2. Data Sheet. SPECIFICATIONS DAC SPECIFICATIONS. Table 1. … |
| 文件格式/大小 | PDF / 960 Kb |
| 文件语言 | 英语 |
AD7294-2. Data Sheet. SPECIFICATIONS DAC SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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AD7294-2 Data Sheet SPECIFICATIONS DAC SPECIFICATIONS
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; TA = −40°C to +105°C, unless otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating; therefore, the DAC output span = 0 V to 5 V.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY1 Resolution 12 Bits Relative Accuracy (INL) ±1 ±3 LSB Differential Nonlinearity (DNL) ±0.3 ±1 LSB Guaranteed monotonic Zero-Code Error 2.5 6 mV Full-Scale Error 10 mV DAC OUTV+ = 5.5 V Offset Error ±4 mV Measured in the linear region, TA = −40°C to +105°C ±2 mV Measured in the linear region, TA = 25°C Offset Error Temperature ±5 ppm/°C Coefficient Gain Error ±0.025 ±0.155 % FSR Gain Error Drift ±5 ppm/°C DAC OUTPUT CHARACTERISTICS Output Voltage Span 0 2 × VREF V 0 V to 5 V for a 2.5 V reference Output Voltage Offset 0 10 V The output voltage span can be positioned in the 0 V to 15 V range; if the OFFSET IN x pin is left floating, the offset = 2/3 × VREF, giving an output of 0 V to 2 × VREF Offset Input Pin Range 0 5 V VOUT = 3 × VOFFSET − 2 × VREF + VDAC DC Input Impedance2 75 kΩ 100 kΩ to VREF, and 200 kΩ to AGND; see Figure 45 Output Voltage Settling Time2 8 µs 1/4 to 3/4 change within 1/2 LSB, measured from last SCL edge Slew Rate2 1.1 V/µs Short-Circuit Current2 40 mA Full-scale current shorted to ground Load Current2 ±10 mA Source and/or sink within 200 mV of supply Capacitive Load Stability2 10 nF RL = ∞ DC Output Impedance2 1 Ω REFERENCE Reference Output Voltage 2.49 2.5 2.51 V ±0.2% maximum at 25°C, AVDD = 5 V Reference Input Voltage Range 0 AVDD − 2 V Input Current 400 480 µA VREF = 2.5 V Input Capacitance2 20 pF VREF Output Impedance2 5 Ω A buffer is required if the reference output is used to drive external loads Reference Temperature 10 25 ppm/°C Coefficient 1 Linearity calculated using a reduced code range: Code 10 to Code 4095. 2 Guaranteed by design and characterization; not production tested. Rev. 0 | Page 4 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide
AD7294-2 Data Sheet SPECIFICATIONS DAC SPECIFICATIONS
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; TA = −40°C to +105°C, unless otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating; therefore, the DAC output span = 0 V to 5 V.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY1 Resolution 12 Bits Relative Accuracy (INL) ±1 ±3 LSB Differential Nonlinearity (DNL) ±0.3 ±1 LSB Guaranteed monotonic Zero-Code Error 2.5 6 mV Full-Scale Error 10 mV DAC OUTV+ = 5.5 V Offset Error ±4 mV Measured in the linear region, TA = −40°C to +105°C ±2 mV Measured in the linear region, TA = 25°C Offset Error Temperature ±5 ppm/°C Coefficient Gain Error ±0.025 ±0.155 % FSR Gain Error Drift ±5 ppm/°C DAC OUTPUT CHARACTERISTICS Output Voltage Span 0 2 × VREF V 0 V to 5 V for a 2.5 V reference Output Voltage Offset 0 10 V The output voltage span can be positioned in the 0 V to 15 V range; if the OFFSET IN x pin is left floating, the offset = 2/3 × VREF, giving an output of 0 V to 2 × VREF Offset Input Pin Range 0 5 V VOUT = 3 × VOFFSET − 2 × VREF + VDAC DC Input Impedance2 75 kΩ 100 kΩ to VREF, and 200 kΩ to AGND; see Figure 45 Output Voltage Settling Time2 8 µs 1/4 to 3/4 change within 1/2 LSB, measured from last SCL edge Slew Rate2 1.1 V/µs Short-Circuit Current2 40 mA Full-scale current shorted to ground Load Current2 ±10 mA Source and/or sink within 200 mV of supply Capacitive Load Stability2 10 nF RL = ∞ DC Output Impedance2 1 Ω REFERENCE Reference Output Voltage 2.49 2.5 2.51 V ±0.2% maximum at 25°C, AVDD = 5 V Reference Input Voltage Range 0 AVDD − 2 V Input Current 400 480 µA VREF = 2.5 V Input Capacitance2 20 pF VREF Output Impedance2 5 Ω A buffer is required if the reference output is used to drive external loads Reference Temperature 10 25 ppm/°C Coefficient 1 Linearity calculated using a reduced code range: Code 10 to Code 4095. 2 Guaranteed by design and characterization; not production tested. Rev. 0 | Page 4 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide