Datasheet AD7294-2 (Analog Devices) - 5

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Data Sheet AD7294-2 ADC SPECIFICATIONS
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to 59.4 V; TA = −40°C to +105°C, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY Resolution 12 Bits Integral Nonlinearity (INL)1 ±0.5 ±1 LSB Differential mode ±0.5 ±1.5 LSB Single-ended or pseudo differential mode Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB Differential, single-ended, and pseudo differential modes Single-Ended Mode Offset Error ±1 ±7 LSB Offset Error Match ±0.4 LSB Gain Error ±0.5 ±4.5 LSB Gain Error Match ±0.4 LSB Differential Mode Positive Gain Error ±1 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±3 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB CONVERSION RATE Conversion Time2 3 μs Autocycle Update Rate2 50 μs Throughput Rate 22.22 kSPS fSCL = 400 kHz ANALOG INPUT3 Single-Ended Input Range 0 VREF V 0 V to VREF mode 0 2 × VREF V 0 V to 2 × VREF mode Pseudo Differential Input Range: V 4 IN+ − VIN− 0 VREF V 0 V to VREF mode 0 2 × VREF V 0 V to 2 × VREF mode Fully Differential Input Range: VIN+ − VIN− −VREF +VREF V 0 V to VREF mode −2 × VREF +2 × VREF V 0 V to 2 × VREF mode Input Capacitance2 30 pF DC Input Leakage Current ±1 µA DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)1 73 dB fIN = 10 kHz sine wave; differential mode 72 dB fIN = 10 kHz sine wave; single-ended and pseudo differential modes Signal-to-Noise and Distortion Ratio 72.5 dB fIN = 10 kHz sine wave; differential mode (SINAD)1 71.5 dB fIN = 10 kHz sine wave; single-ended and pseudo differential modes Total Harmonic Distortion (THD)1 −81 dB fIN = 10 kHz sine wave; differential mode −79 dB fIN = 10 kHz sine wave; single-ended and pseudo differential modes Spurious-Free Dynamic Range (SFDR)1 −81 dB fIN = 10 kHz sine wave; differential mode −79 dB fIN = 10 kHz sine wave; single-ended and pseudo differential modes Channel-to-Channel Isolation2 −90 dB fIN = 0.5 Hz to 100 kHz Rev. 0 | Page 5 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide