Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 7

制造商Analog Devices
描述Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management
页数 / 页39 / 7 — Data Sheet. ADuCM3027/. ADuCM3029. ADC SPECIFICATIONS. Table 7. …
修订版B
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Data Sheet. ADuCM3027/. ADuCM3029. ADC SPECIFICATIONS. Table 7. Parameter1, 2 Min. Typ3 Max. Unit. Test. Conditions/Comments

Data Sheet ADuCM3027/ ADuCM3029 ADC SPECIFICATIONS Table 7 Parameter1, 2 Min Typ3 Max Unit Test Conditions/Comments

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Data Sheet ADuCM3027/ ADuCM3029 ADC SPECIFICATIONS Table 7. Parameter1, 2 Min Typ3 Max Unit Test Conditions/Comments
INTEGRAL NONLINEARITY ERROR 64-Lead LFCSP ±1.6 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 64-Lead LFCSP ±1.4 LSB 3.0 V (VBAT)/2.5 V (internal/external VREF)4 54-Ball WLCSP ±1.8 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 DIFFERENTIAL NONLINEARITY ERROR 64-Lead LFCSP −0.7 to +1.15 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 64-Lead LFCSP −0.7 to +1.1 LSB 3.0 V (VBAT)/2.5 V (internal/external VREF)4 54-Ball WLCSP −0.75 to +1.2 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 OFFSET ERROR 64-Lead LFCSP ±0.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 64-Lead LFCSP ±0.5 LSB 3.0 V (VBAT)/2.5 V (external VREF)4 54-Ball WLCSP ±0.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 GAIN ERROR 64-Lead LFCSP ±2.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 64-Lead LFCSP ±0.5 LSB 3.0 V (VBAT)/2.5 V (external VREF)4 54-Ball WLCSP ±3.0 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 VBAT_ADC CURRENT (IVBAT_ADC)5 64-Lead LFCSP 104 μA 1.8 V (VBAT)/1.25 V (internal VREF)6 64-Lead LFCSP 131 μA 3.0 V (VBAT)/2.5 V (internal VREF)6 54-Ball WLCSP 108 μA 1.8 V (VBAT)/1.25 V (internal VREF)6 INTERNAL REFERENCE VOLTAGE 1.25 V Internal reference, 1.25 V selected 2.50 V Internal reference, 2.5 V selected INTEGRAL NONLINEARITY ERROR 64-Lead LFCSP 1.22 1.25 1.275 V 1.25 V (internal)7 64-Lead LFCSP 2.45 2.5 2.545 V 2.5 V (internal) 54-Ball WLCSP 1.22 1.25 1.275 V 1.25 V (internal) 54-Ball WLCSP 2.45 2.5 2.545 V 2.5 V (internal) ADC SAMPLING FREQUENCY (fS)8 0.01 1.8 MSPS 1 The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs. 2 The specifications are characterized after performing internal ADC offset calibration. 3 TJ = 25°C. 4 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode, 400,000 samples end point method used. 5 Current consumption from VBAT_ADC supply when ADC is performing the conversion. 6 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode. 7 No load current, CL = 0.1 μF and 4.7 μF, reference buffer low power mode is enabled. 8 Effects of analog source impedance must be considered when selecting ADC sampling frequency. Rev. B | Page 7 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide