Datasheet ADRV9002 (Analog Devices) - 3

Preliminary Technical Data ADRV9002 FUNCTIONAL BLOCK DIAGRAM RX1 I S RX2 S RX1A+ DS RT RX1A– V ADC O DDC, DEC, L P RX2A+ QEC, R A RX2A– DC-OFFSET, I O OFFSET TONE-DET. S RX1B+ DACs S DAT RX1B– S O RX RX2B+ ADC CM RX2B– DIGITAL TX1 TX2 I S S TX1+ DAC TX1– DS V RT L O TX2+ P INTs, QEC, R TX2– A LOL, DPD I O S AT D DAC S S X O T CM GPIO s ARM4 AUXADC IO AUXDAC MUX MUX CALIBRATION GP CONTROL, RF GAIN CONTROL, L RF X PLL 2 SLEEP CONTROL, RO PLL 1 X DPD, MU NT /2 GPIO, EXT_RXLO MU /2 BB CO CTRL, EXT_TXLO PLL SPI T R DEV_CLK SPI
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00 3- 2466 Figure 1. Rev. PrA | Page 3 of 71 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TRANSMITTER SPECIFICATIONS RECEIVER SPECIFICATIONS INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK DIGITAL INTERFACES AND AUXILIARY CONVERTERS POWER SUPPLY SPECIFICATIONS CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES) Sleep Mode (Typical Values) TDD Operation (Typical Values) FDD Operation (Typical Values) TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRV2009 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 30 MHZ BAND 470 MHZ BAND 900 MHZ BAND 2400 MHZ BAND 3500 MHZ BAND 5800 MHZ BAND PHASE NOISE THEORY OF OPERATION TRANSMITTER RECEIVER Monitor Mode DPD Receiver as an Observation Receiver CLOCK INPUT SYNTHESIZERS RF PLL Baseband PLL (PLL) SPI INTERFACE GPIO PINS Digital GPIO Inputs/Outputs (DGPIO) Analog GPIO Inputs/Outputs (AGPIO) AUXILLARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs Outputs (AUXDAC_x) JTAG BOUNDARY SCAN APPLICATIONS INFORMATION POWER SUPPLY SEQUENCE DIGITAL DATA INTERFACE CSSI CSSI Receive CSSI Transmit LSSI OUTLINE DIMENSIONS