Datasheet ADRV9002 (Analog Devices) - 71
制造商 | Analog Devices |
描述 | Dual Narrow/Wideband RF Transceiver |
页数 / 页 | 71 / 71 — Preliminary Technical Data. ADRV9002. OUTLINE DIMENSIONS |
修订版 | PrA |
文件格式/大小 | PDF / 1.6 Mb |
文件语言 | 英语 |
Preliminary Technical Data. ADRV9002. OUTLINE DIMENSIONS

该数据表的模型线
文件文字版本
Preliminary Technical Data ADRV9002 OUTLINE DIMENSIONS
Figure 205. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-196-14) Dimensions shown in millimeters
©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR24663-7/20(PrA)
Rev. PrA | Page 71 of 71 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TRANSMITTER SPECIFICATIONS RECEIVER SPECIFICATIONS INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK DIGITAL INTERFACES AND AUXILIARY CONVERTERS POWER SUPPLY SPECIFICATIONS CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES) Sleep Mode (Typical Values) TDD Operation (Typical Values) FDD Operation (Typical Values) TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRV2009 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 30 MHZ BAND 470 MHZ BAND 900 MHZ BAND 2400 MHZ BAND 3500 MHZ BAND 5800 MHZ BAND PHASE NOISE THEORY OF OPERATION TRANSMITTER RECEIVER Monitor Mode DPD Receiver as an Observation Receiver CLOCK INPUT SYNTHESIZERS RF PLL Baseband PLL (PLL) SPI INTERFACE GPIO PINS Digital GPIO Inputs/Outputs (DGPIO) Analog GPIO Inputs/Outputs (AGPIO) AUXILLARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs Outputs (AUXDAC_x) JTAG BOUNDARY SCAN APPLICATIONS INFORMATION POWER SUPPLY SEQUENCE DIGITAL DATA INTERFACE CSSI CSSI Receive CSSI Transmit LSSI OUTLINE DIMENSIONS