Datasheet ADCMP600, ADCMP601, ADCMP602 (Analog Devices) - 10

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ADCMP600/ADCMP601/ADCMP602 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING
This delay is measured to the 50% point for the supply in use; The ADCMP600/ADCMP601/ADCMP602 comparators are very therefore, the fastest times are observed with the VCC supply at high speed devices. Despite the low noise output stage, it is essential 2.5 V, and larger values are observed when driving loads that to use proper high speed design techniques to achieve the specified switch at other levels. performance. Because comparators are uncompensated amplifiers, When duty cycle accuracy is critical, the logic being driven feedback in any phase relationship is likely to cause oscil ations or should switch at 50% of VCC and load capacitance should be undesired hysteresis. Of critical importance is the use of low minimized. When in doubt, it is best to power VCCO or the impedance supply planes, particularly the output supply plane entire device from the logic supply and rely on the input PSRR (V and CMRR to reject noise. CCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest Overdrive and input slew rate dispersions are not significantly inductance return path for switching currents ensures the best affected by output loading and V possible performance in the target application. CC variations. The TTL-/CMOS-compatible output stage is shown in the It is also important to adequately bypass the input and output simplified schematic diagram (Figure 17). Because of its supplies. Multiple high quality 0.01 µF bypass capacitors should inherent symmetry and general y good behavior, this output be placed as close as possible to each of the VCCI and VCCO supply stage is readily adaptable for driving various filters and other pins and should be connected to the GND plane with redundant unusual loads. vias. At least one of these should be placed to provide a physical y short return path for output currents flowing back from ground
VLOGIC
to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic
A1 Q1
layout inductance should also be strictly control ed to maximize the effectiveness of the bypass at high frequencies. If the package allows and the input and output supplies have
+IN OUTPUT
been connected separately such that V
AV
CCI ≠ VCCO, care should be
–IN
taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should never be connected between them. It is recommended that the GND plane separate the VCCI
A2 Q2
and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take 014
GAIN STAGE OUTPUT STAGE
advantage of the additional bypass capacitance from each 05914- respective supply to the ground plane. This enhances the Figure 17. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply
USING/DISABLING THE LATCH FEATURE
operation such that VCCI = VCCO, coupling between the two supplies The latch input is designed for maximum versatility. It can is unavoidable; however, careful board placement can help keep safely be left floating for fixed hysteresis or be tied to VCC to output return currents away from the inputs. remove the hysteresis, or it can be driven low by any standard
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
TTL/CMOS device as a high speed latch. Specified propagation delay performance can be achieved only In addition, the pin can be operated as a hysteresis control pin by keeping the capacitive load at or below the specified minimums. with a bias voltage of 1.25 V nominal and an input resistance of The outputs of the devices are designed to directly drive one approximately 7000 Ω. This allows the comparator hysteresis to Schottky TTL or three low power Schottky TTL loads or the be easily and accurately controlled by either a resistor or an equivalent. For large fan outputs, buses, or transmission lines, inexpensive CMOS DAC. use an appropriate buffer to maintain the excellent speed and Hysteresis control and latch mode can be used together if an stability of the comparator. open drain, an open collector, or a three-state driver is connected With the rated 5 pF load capacitance applied, more than half of parallel to the hysteresis control resistor or current source. the total device propagation delay is output stage slew time, Due to the programmable hysteresis feature, the logic threshold even at 2.5 V VCC. Because of this, the total prop delay decreases of the latch pin is approximately 1.1 V regardless of VCC. as VCCO decreases, and instability in the power supply may appear as excess delay dispersion. Rev. A | Page 10 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide