Datasheet ADCMP572, ADCMP573 (Analog Devices)

Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators Data Sheet ADCMP572/ ADCMP573 FEATURES FUNCTIONAL BLOCK DIAGRAM 3.3 V/5.2 V single-supply operation V V CCI CCO 150 ps propagation delay 15 ps overdrive and slew rate dispersion VTP TERMINATION 8 GHz equivalent input rise time bandwidth V 80 ps minimum pulse width P NONINVERTING INPUT Q OUTPUT ADCMP572 CML/ 35 ps typical output rise/fall ADCMP573 RSPECL V 10 ps deterministic jitter (DJ) N INVERTING Q OUTPUT INPUT 200 fs random jitter (RJ) On-chip terminations at both input pins VTN TERMINATION Robust inputs with no output phase reversal LE INPUT Resistor-programmable hysteresis HYS LE INPUT
04409-025
Differential latch control
Figure 1.
Extended industrial −40°C to +125°C temperature range APPLICATIONS Clock and data signal restoration and level shifting Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators provided at both inputs with the optional capability to be left fabricated on Analog Devices, Inc., proprietary XFCB3 Silicon open (on an individual pin basis) for applications requiring Germanium (SiGe) bipolar process. The ADCMP572 features high impedance inputs. CML output drivers and latch inputs, and the ADCMP573 The CML output stage is designed to directly drive 400 mV into features reduced swing PECL (RSPECL) output drivers and 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. latch inputs. The RSPECL output stage is designed to drive 400 mV into 50 Ω Both devices offer 150 ps propagation delay and 80 ps terminated to VCCO − 2 V and is compatible with several commonly minimum pulse width for 10 Gbps operation with 200 fs rms used PECL logic families. The comparator input stage offers robust random jitter (RJ). Overdrive and slew rate dispersion are protection against large input overdrive, and the outputs do not typically less than 15 ps. phase reverse when the valid input signal range is exceeded. A flexible power supply scheme allows both devices to operate High speed latch and programmable hysteresis features are also with a single 3.3 V positive supply and a −0.2 V to +1.2 V input provided. signal range or with split input/output supplies to support a The ADCMP572 and ADCMP573 are available in a 16-lead wider −0.2 V to +3.2 V input signal range and an independent LFCSP package and have been characterized over an extended range of output levels. 50 Ω on-chip termination resistors are industrial temperature range of −40°C to +125°C.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENTS TYPICAL APPLICATION CIRCUITS TIMING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE