Datasheet ADCMP572, ADCMP573 (Analog Devices) - 10

link to page 10 link to page 10
ADCMP572/ADCMP573 Data Sheet
VCCO is the signal return for the output stage and VCCO pins
COMPARATOR PROPAGATION
should of course be connected to a supply plane for maximum
DELAY DISPERSION
performance. The ADCMP572/ADCMP573 comparators are designed to
OPTIMIZING HIGH SPEED PERFORMANCE
reduce propagation delay dispersion over a wide input overdrive As with any high speed comparator, proper design and layout range of 5 mV to 500 mV. Propagation delay dispersion is variation techniques are essential to obtaining the specified performance. in the propagation delay that results from a change in the degree of Stray capacitance, inductance, inductive power and ground overdrive or slew rate (how far or how fast the input signal impedances, or other layout issues can severely limit performance exceeds the switching threshold). and often cause oscillation. Discontinuities along input and Propagation delay dispersion is a specification that becomes output transmission lines can severely limit the specified pulse important in high speed, time-critical applications such as data width dispersion performance. communication, automatic test and measurement, instrumenta- For applications working in a 50 Ω environment, input and tion, and event driven applications such as pulse spectroscopy, output matching has a significant impact on data dependent (or nuclear instrumentation, and medical imaging. Dispersion is deterministic) jitter (DJ) and on pulse width dispersion defined as the variation in propagation delay as the input over- performance. The ADCMP572/ADCMP573 comparators drive conditions vary (Figure 17 and Figure 18). For the provide internal 50 Ω termination resistors for both the V ADCMP572/ADCMP573, dispersion is typically <15 ps P and V because the overdrive varies from 10 mV to 500 mV, and the N inputs, and the ADCMP572 provides 50 Ω back terminated outputs. The return side for each input termination is pinned input slew rate varies from 2 V/ns to 10 V/ns. This specification out separately with the V applies for both positive and negative signals since the TP and VTN pins, respectively. If a 50 Ω termination is desired at one or both of the V ADCMP572/ADCMP573 has substantially equal delays for P/VN inputs, then the V either positive going or negative going inputs. TP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as required. The
500mV OVERDRIVE
termination potential should be carefully bypassed using high quality bypass capacitors as discussed earlier to prevent undesired
INPUT VOLTAGE
aberrations on the input signal due to parasitic inductance in
10mV OVERDRIVE
the circuit board layout. If a 50 Ω input termination is not desired, either one or both of the V
VN ± VOS
TP/VTN termination pins can be left disconnected. In this case, the pins should be left floating with no external pull-downs or bypassing capacitors.
DISPERSION
When leaving an input termination disconnected, the internal
Q/Q OUTPUT
resistor acts as a small stub on the input transmission path and 04409-0-027 can cause problems for very high speed inputs. Reflections Figure 17. Propagation Delay—Overdrive Dispersion should then be expected from the comparator inputs because
INPUT VOLTAGE
they no longer provide matched impedance to the input path
1V/ns
leading to the device. In this case, it is important to back match
VN ± VOS
the drive source impedance to the input transmission path to
10V/ns
minimize multiple reflections. For applications in which the comparator is very close to the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator
DISPERSION
might cause an undesirable degradation in bandwidth at the
Q/Q OUTPUT
04409-0-028 input, therefore degrading the overall response. Although the Figure 18. Propagation Delay—Slew Rate Dispersion ADCMP572/ADCMP573 comparators have been designed to minimize input capacitance, some parasitic capacitance is inevitable. It is therefore recommended that the drive source impedance be no more than 50 Ω for best high speed performance. Rev. B | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENTS TYPICAL APPLICATION CIRCUITS TIMING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE