Datasheet ADP1765 (Analog Devices) - 5

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Data Sheet ADP1765 ABSOLUTE MAXIMUM RATINGS Table 4.
characterization parameters are not the same as thermal
Parameter Rating
resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in VIN to GND −0.3 V to +2.16 V thermal resistance, θ EN to GND −0.3 V to +3.96 V JB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from VOUT to GND −0.3 V to VIN the package, factors that make Ψ SENSE to GND −0.3 V to V JB more useful in real-world IN applications. VREG to GND −0.3 V to VIN REFCAP to GND −0.3 V to VIN
THERMAL RESISTANCE/PARAMETER
VADJ to GND −0.3 V to VIN Values shown in Table 5 are calculated in compliance with SS to GND −0.3 V to VIN JEDEC standards for thermal reporting. θJA is the natural PG to GND −0.3 V to +3.96 V convection junction to ambient thermal resistance measured in a Storage Temperature Range −65°C to +150°C one cubic foot sealed enclosure. θJC is the junction to case thermal Operating Temperature Range −40°C to +125°C resistance. θJB is the junction to board thermal resistance. ΨJB is Operating Junction Temperature 125°C the junction to board thermal characterization parameter. ΨJT is Lead Temperature (Soldering, 10 sec) 300°C the junction to top thermal characterization parameter. Stresses at or above those listed under Absolute Maximum In applications where high maximum power dissipation exists, Ratings may cause permanent damage to the product. This is a close attention to thermal board design is required. Thermal stress rating only; functional operation of the product at these resistance/parameter values may vary, depending on the PCB or any other conditions above those indicated in the operational material, layout, and environmental conditions. section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may
Table 5. Thermal Resistance/Parameter
affect product reliability.
Package Type θ THERMAL DATA JA θJC θJB ΨJB ΨJT Unit
CP-16-481 40.65 7.47 17.38 12.9 0.85 °C/W Absolute maximum ratings apply individually only, not in 1 Thermal resistance/parameter simulated values are based on a JEDEC 2S2P combination. The ADP1765 can be damaged when the junction thermal test board for ΨJT, ΨJB, θJA and θJB and a JEDEC 1S0P thermal test board temperature limits are exceeded. The use of appropriate thermal for θJC with four thermal vias. See JEDEC JESD51-12. management techniques is recommended to ensure that the
ESD CAUTION
maximum junction temperature does not exceed the limits shown in Table 4. Use the fol owing equation to calculate the junction temperature (TJ) from the board temperature (TBOARD) or package top temperature (T TOP) TJ = TBOARD + (PD × ΨJB) TJ = TTOP + (PD × Ψ JT) ΨJB is the junction to board thermal characterization parameter and ΨJT is the junction to top thermal characterization parameter with units of °C/W. Ψ JB of the package is based on modeling and calculation using a 4-layer board. JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal Rev. A | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUITS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE/PARAMETER ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START FUNCTION ADJUSTABLE OUTPUT VOLTAGE ENABLE FEATURE POWER-GOOD (PG) FEATURE APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION PARALLELING ADP1765 DEVICES FOR HIGH CURRENT APPLICATIONS THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE