Datasheet ADP1761 (Analog Devices) - 5

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Data Sheet ADP1761 ABSOLUTE MAXIMUM RATINGS Table 4.
ΨJB of the package is based on modeling and calculation using a 4-layer board. JESD51-12, Guidelines for Reporting and Using
Parameter Rating
Electronic Package Thermal Information, states that thermal VIN to GND −0.3 V to +2.16 V characterization parameters are not the same as thermal EN to GND −0.3 V to +3.96 V resistances. Ψ VOUT to GND −0.3 V to VIN JB measures the component power flowing through multiple thermal paths rather than a single path as in SENSE to GND −0.3 V to VIN thermal resistance, θ VREG to GND −0.3 V to VIN JB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation REFCAP to GND −0.3 V to VIN from the package, factors that make ΨJB more useful in real- VADJ to GND −0.3 V to VIN world applications. SS to GND −0.3 V to VIN PG to GND −0.3 V to +3.96 V
THERMAL RESISTANCE/PARAMETER
Storage Temperature Range −65°C to +150°C Values shown in Table 5 are calculated in compliance with Operating Temperature Range −40°C to +125°C JEDEC standards for thermal reporting. θJA is the natural Operating Junction Temperature 125°C convection junction to ambient thermal resistance measured in a Lead Temperature (Soldering, 10 sec) 300°C one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. θJB is the junction to board thermal resistance. ΨJB is Stresses at or above those listed under Absolute Maximum the junction to board thermal characterization parameter. ΨJT is Ratings may cause permanent damage to the product. This is a the junction to top thermal characterization parameter. stress rating only; functional operation of the product at these In applications where high maximum power dissipation exists, or any other conditions above those indicated in the close attention to thermal board design is required. Thermal operational section of this specification is not implied. resistance/parameter values may vary, depending on the PCB Operation beyond the maximum operating conditions for material, layout, and environmental conditions. extended periods may affect product reliability.
THERMAL DATA Table 5. Thermal Resistance/Parameter Package
Absolute maximum ratings apply individually only, not in
Type θJA θJB θJC-T θJC-B ΨJB ΨJT Unit
combination. The ADP1761 can be damaged when the junction CP-16-221 50.95 29.31 49.53 8.53 29.31 0.3 °C/W temperature limits are exceeded. The use of appropriate thermal 1 Thermal resistance/parameter simulated values are based on a JEDEC 2S2P management techniques is recommended to ensure that the thermal test board for ΨJT, ΨJB, θJA and θJB and a JEDEC 1S0P thermal test maximum junction temperature does not exceed the limits shown board for θJC with four thermal vias. See JEDEC JESD51-12. in Table 4.
ESD CAUTION
Use the following equation to calculate the junction temperature (TJ) from the board temperature (TBOARD) or package top temperature (TTOP) TJ = TBOARD + (PD × ΨJB) TJ = TTOP + (PD × ΨJT) ΨJB is the junction to board thermal characterization parameter and ΨJT is the junction to top thermal characterization parameter with units of °C/W. Rev. C | Page 5 of 18 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitor: Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance/Parameter ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Soft Start Function Adjustable Output Voltage Enable Feature Power-Good (PG) Feature Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Current-Limit and Thermal Overload Protection Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide