Datasheet ADP1761 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 1 A, Low VIN, Low Noise, CMOS Linear Regulator |
| 页数 / 页 | 18 / 6 — ADP1761. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SEN. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 794 Kb |
| 文件语言 | 英语 |
ADP1761. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SEN. VIN 1. 12 VOUT. VIN 2. 11 VOUT. VIN 3. TOP VIEW. 10 VOUT
该数据表的模型线
文件文字版本
ADP1761 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SE EN PG SS SEN 61 51 41 31 VIN 1 12 VOUT VIN 2 11 VOUT ADP1761 VIN 3 TOP VIEW 10 VOUT (Not to Scale) VIN 4 9 VOUT 5 6 7 8 P D EG CA ADJ F GN VR V RE NOTES 1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO GND. IT IS RECOMMENDED THAT THIS PAD BE CONNECTED TO A GROUND
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PLANE ON THE PCB. THE EXPOSED PAD IS ON THE BOTTOM OF THE PACKAGE.
919 12 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 to 4 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be connected to the source supply. 5 REFCAP Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to ground. 6 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. 7 GND Ground. 8 VADJ Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating. 9 to 12 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins must be connected to the load. 13 SENSE Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the load. 14 SS Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms. 15 PG Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output voltage, the PG pin immediately transitions low. 16 EN Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For automatic startup, connect the EN pin to the VIN pin. EP Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to a ground plane on the PCB. The exposed pad is on the bottom of the package. Rev. C | Page 6 of 18 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitor: Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance/Parameter ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Soft Start Function Adjustable Output Voltage Enable Feature Power-Good (PG) Feature Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Current-Limit and Thermal Overload Protection Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide
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PLANE ON THE PCB. THE EXPOSED PAD IS ON THE BOTTOM OF THE PACKAGE.
919 12 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 to 4 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be connected to the source supply. 5 REFCAP Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to ground. 6 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. 7 GND Ground. 8 VADJ Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating. 9 to 12 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins must be connected to the load. 13 SENSE Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the load. 14 SS Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms. 15 PG Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output voltage, the PG pin immediately transitions low. 16 EN Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For automatic startup, connect the EN pin to the VIN pin. EP Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to a ground plane on the PCB. The exposed pad is on the bottom of the package. Rev. C | Page 6 of 18 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitor: Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance/Parameter ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Soft Start Function Adjustable Output Voltage Enable Feature Power-Good (PG) Feature Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Current-Limit and Thermal Overload Protection Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide