Datasheet ADP5030 (Analog Devices) - 3

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ADP5030 SPECIFICATIONS
VIN1 = (VOUT2 + 0.5 V) or 2.5 V (whichever is greater), VIN1 ≥ VIN2 ≥ VIN3, IOUT1 = IOUT2 = 10 mA, TA = 25°C, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE1 VIN1 TJ = −40°C to +125°C 2.5 5.5 V VIN2 TJ = −40°C to +125°C 1.1 1.8 3.6 V VIN3 TJ = −40°C to +125°C 1.1 VIN2 V OPERATING SUPPLY CURRENT WITH IGND 60 μA BOTH REGULATORS ON IOUT1, IOUT2 = 0 μA 60 μA IOUT1, IOUT2 = 0 μA, TJ = −40°C to +125°C 120 μA IOUT1, IOUT2 = 10 mA 70 μA IOUT1, IOUT2 = 10 mA, TJ = −40°C to +125°C 140 μA IOUT1, IOUT2 = 200 mA 120 μA IOUT1, IOUT2 = 200 mA, TJ = −40°C to +125°C 220 μA SHUTDOWN CURRENT EN1 = GND, GPIN2 = GPIN1 = VIH From VIN1 Pin IIN1-SD VIN1 = 5.5 V, TJ = −40°C to +125°C 0.4 2.0 μA From VIN2 Pin IIN2-SD VIN2 = 1.8 V, TJ = −40°C to +85°C 0.4 2.0 μA From VIN3 Pin IIN3-SD VIN3 = 1.2 V, TJ = −40°C to +125°C 0.2 1.5 μA FIXED OUTPUT VOLTAGE ACCURACY VOUT1, VOUT2 −0.7 +0.7 % 100 μA < IOUT1, IOUT2 < 200 mA, VIN1 = (VOUT2 + 0.5 V) −2.0 +1 % to 5.5 V, TJ = −40°C to +125°C LINE REGULATION ∆VOUT/∆VIN VIN1 = (VOUT2 + 0.5 V) to 5.5 V 0.01 %/V VIN1 = (VOUT2 + 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/V LOAD REGULATION ∆VOUT/∆IOUT IOUT1, IOUT2 = 1 mA to 200 mA 0.001 %/mA IOUT1, IOUT2 = 1 mA to 200 mA, TJ = −40°C to +125°C 0.003 %/mA DROPOUT VOLTAGE2 VDROPOUT VOUT2 = 2.8 V IOUT1, IOUT2 = 10 mA 9 mV IOUT1, IOUT2 = 10 mA, TJ = −40°C to +125°C 13 mV IOUT1, IOUT2 = 200 mA 175 mV IOUT1, IOUT2 = 200 mA, TJ = −40°C to +125°C 250 mV START-UP TIME3 tSTART-UP VOUT2 = 2.8 V 240 μs VOUT1 = 1.2 V 120 μs CURRENT-LIMIT THRESHOLD4 ILIMIT1, ILIMIT2 240 300 440 mA LOAD SWITCH OUTPUT CURRENT IOUT3 500 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 155 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C EN1, MSEL INPUTS EN1, MSEL Input Logic High VIH1 2.5 V ≤ VIN1 ≤ 5.5 V 1.2 V EN1, MSEL Input Logic Low VIL1 2.5 V ≤ VIN1 ≤ 5.5 V 0.4 V EN1, MSEL Input Leakage Current ILEAKAGE1 EN1 = MSEL = VIN1 or GND 0.2 μA EN1 = MSEL = VIN1 or GND, TJ = −40°C to +125°C 1 μA EN2 INPUT EN2 Input Logic High VIH2 1.2 V ≤ VIN2 ≤ 3.6 V 0.65 × VIN2 V EN2 Input Logic Low VIL2 1.2 V ≤ VIN2 ≤ 3.6 V 0.35 × VIN2 V EN2 Input Leakage Current ILEAKAGE2 EN2 = VIN2 or GND 0.2 μA EN2 = VIN2 or GND, TJ = −40°C to +125°C 1 μA UNDERVOLTAGE LOCKOUT (VIN1) UVLO Input Voltage Rising UVLORISE 2.45 V Input Voltage Falling UVLOFALL 2.2 V Hysteresis UVLOHYS 100 mV OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN1 = 5 V, VOUTx = 2.8 V 50 μV rms 10 Hz to 100 kHz, VIN1 = 3.6 V, VOUTx = 1.2 V 27 μV rms Rev. B | Page 3 of 3 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION LDO2 AND LOAD SWITCH ACTIVATION LOGIC SEQUENCING CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE