Datasheet ADP5030 (Analog Devices) - 4

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ADP5030 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR VIN1 = 2.5 V, VOUT1 = 1.2 V, IOUT = 100 mA 100 Hz 76 dB 1 kHz 76 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB VIN1 = 3.8 V, VOUT2 = 2.8 V, IOUT = 100 mA 100 Hz 68 dB 1 kHz 68 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB LOAD SWITCH VIN2 to VOUT3 Resistance RDSON ILOAD = 200 mA, EN2 = VIH2, MSEL = GPIN1 = GND VIN2 = 3.6 V 70 mΩ VIN2 = 2.5 V 80 mΩ VIN2 = 1.8 V 100 130 mΩ VIN2 = 1.8 V, TJ = −40°C to +125°C 160 mΩ Turn-On Times VIN2 = 1.8 V, ILOAD = 100 mA, CLOAD = 0.1 μF, EN2 = VIH2, MSEL = GPIN1 = GND Turn-On Delay Time tON_DLY EN2 rising to 10% of turn-on value 5 15 μs Turn-On Rise Time tON_RISE VOUT3 rising from 10% to 90% of turn-on value 8 12 μs LEVEL SHIFTER VIN1 = 3.6 V, 1.2 V ≤ VIN3 ≤ 3.6 V, TJ = −40°C to +125°C GPIN1 Input Logic High VIH 0.65 × VIN3 V GPIN1 Input Logic Low VIL 0.35 × VIN3 V GPOUT1 Output Logic High VOH IOH = 2 mA, VIN2 = 1.8 V 1.6 V GPOUT1 Output Logic Low VOL IOL = 1 mA, VIN2 = 1.8 V 0.16 V GPOUT1 Output Logic Low VOL IOL = 2 mA, VIN2 = 1.8 V 0.31 V GPIN1 to GPOUT1 Propagation tPHL, tPLH CLOAD = 30 pF, RLOAD = 1 MΩ, VIN2 = 1.8 V 20 ns Delay GPIN2, GPIN3 Input Logic High VIH 0.65 × VIN3 V GPIN2, GPIN3 Input Logic Low VIL 0.35 × VIN3 V GPOUT2, GPOUT3 Output Logic High VOH IOH = 2 mA, VIN3 = 1.2 V 0.95 V GPOUT2, GPOUT3 Output Logic Low VOL IOL = 1 mA, VIN3 = 1.2 V 0.17 V IOL = 2 mA, VIN3 = 1.2 V 0.33 V GPIN2, GPIN3 to GPOUT2, GPOUT3 tPHL, tPLH CLOAD = 30 pF, RLOAD = 1 MΩ 20 ns Propagation Delay GPIN1, GPIN2, GPIN3 Input Leakage ILEAKAGE-GPIN GPIN1, GPIN2, GPIN3 = VIN3 or GND, TA = 25°C 0.1 μA Current GPIN1, GPIN2, GPIN3 = VIN3 or GND 1 μA 1 VIN2 minimum supply voltage is 1.1 V or VIN3, whichever is greater. VIN2 maximum supply voltage is 3.6 V or VIN1, whichever is smaller. 2 Dropout voltage is the input-to-output voltage differential when the input voltage is set to the nominal output voltage. It applies only to output voltages above 2.5 V. 3 Start-up time is defined as the time between the rising edge of EN1 to VOUT1 being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE (LDO1, LDO2)1 CMIN TA = –40°C to +125°C 0.70 μF CAPACITOR ESR RESR TA = –40°C to +125°C 0.001 1 Ω 1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during capacitor selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. B | Page 4 of 4 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION LDO2 AND LOAD SWITCH ACTIVATION LOGIC SEQUENCING CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE