Datasheet ADL5391 (Analog Devices)

DC to 2.0 GHz Multiplier Data Sheet ADL5391 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrafast symmetric multiplier YMNS YPLS GADJ Function: VW = α × (VX × VY)/1 V + VZ Unique design ensures absolute XY-symmetry XPLS ZMNS Identical X and Y amplitude/timing responses XMNS ZPLS Adjustable gain scaling, α WPLS DC-coupled throughout, 3 dB bandwidth of 2 GHz ENBL WMNS Fully differential inputs, may be used single ended Low noise, high linearity VMID ADL5391 Accurate, temperature stable gain scaling W = αXY/1V+Z
001
Single-supply operation (4.5 V to 5.5 V at 130 mA) COMM VPOS
06059-
Low current power-down mode
Figure 1.
16-lead LFCSP APPLICATIONS Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control GENERAL DESCRIPTION
The ADL5391 draws on three decades of experience in are ac-coupled, their nominal voltage will be VPOS/2. These input advanced analog multiplier products. It provides the same interfaces each present a differential 500 Ω input impedance up to general mathematical function that has been field proven to approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain provide an exceptional degree of versatility in function synthesis. scaling input, GADJ, can be used for fine adjustment of the gain scaling constant (α) about unity. VW = α × (VX × VY)/ 1 V + VZ The differential output can swing ±2 V about the VPOS/2 The most significant advance in the ADL5391 is the use of a common-mode and can be taken in a single-ended fashion as new multiplier core architecture, which differs markedly from well. The output common mode is designed to interface directly the conventional form that has been in use since 1970. The to the inputs of another ADL5391. Light dc loads can be ground conventional structure that employs a current mode, translinear referenced; however, ac-coupling of the outputs is recommended core is fundamentally asymmetric with respect to the X and Y for heavy loads. inputs, leading to relative amplitude and timing misalignments that are problematic at high frequencies. The new multiplier core The ENBL pin al ows the ADL5391 to be disabled quickly to a eliminates these misalignments by offering symmetric signal standby mode. It operates off supply voltages from 4.5 V to 5.5 V paths for both X and Y inputs. The Z input allows a signal to be while consuming approximately 130 mA. added directly to the output. This can be used to cancel a carrier or to apply a static offset voltage. The ADL5391 is fabricated on Analog Devices, Inc. proprietary, high performance, 65 GHz, SOI complementary, SiGe bipolar The fully differential X, Y, and Z input interfaces are operational IC process. It is available in a 16-lead, RoHS compliant, LFCSP over a ±2 V range, and they can be used in single-ended fashion. and operates over a −40°C to +85°C temperature range. The user can apply a common mode at these inputs to vary Evaluation boards are available. from the internal y set VPOS/2 down to ground. If these inputs
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Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Theory Calibration Basic Connections Multiplier Connections Matching the Input/Output Wideband Voltage-Controlled Amplifier/Amplitude Modulator Squaring and Frequency Doubling Use as a Detector Evaluation Board Outline Dimensions Ordering Guide