Datasheet ADL5391 (Analog Devices) - 10

link to page 7 link to page 7 link to page 7
ADL5391 Data Sheet THEORY OF OPERATION BASIC THEORY
The small-signal bandwidth from the inputs X, Y, and Z to The multiplication of two analog variables is a fundamental the output W is a single-pole response. The pole is inversely signal processing function that has been around for decades. By proportional to α. For α = 1 (GADJ floating), the bandwidth is convention, the desired transfer function is given by about 2 GHz; for α > 1, the bandwidth is reduced; and for α < 1, the bandwidth is increased. W = αXY/U + Z (1) where: All input ports, X, Y, and Z, are differential and internally X and Y are the multiplicands. biased to midsupply, VPOS/2. The differential input impedance is U is the multiplier scaling factor. 500 Ω up to 100 MHz, rolling off to 50 Ω at 2 GHz. All inputs α is the multiplier gain. can be driven in single-ended fashion and can be ac-coupled. In W is the product output. dc-coupled operation, the inputs can be biased to a common Z is a summing input. mode that is lower than VPOS/2. The bias current flowing out of the input pins to accommodate the lower common mode is Al the variables and the scaling factor have the dimension of volts. subtracted from the 50 mA total available from the internal reference V In the past, analog multipliers, such as the AD835, were POS/2 at the VREF pin. Each input pin presents an equivalent 250 Ω dc resistance to V implemented almost exclusively with a Gilbert Cell topology POS/2. If all six input pins sit 1 V below V or a close derivative. The inherently asymmetric signal paths POS/2, a total of 6 × 1 V/250 Ω = 24 mA must flow internal y from VREF to the input pins. for X and Y inevitably create amplitude and delay imbalances between X and Y. In the ADL5391, the novel multiplier core
Calibration
provides absolute symmetry between X and Y, minimizing The dc offset of the ADL5391 is approximately 20 mV but scaling and phasing differences inherent in the Gilbert Cell. changes over temperature and has variation from part to part The simplified block diagram of the ADL5391 shows a main (see Figure 4). It is generally not of concern unless the ADL5391 multiplier cell that receives inputs X and Y and a second is operated down to dc (close to the point X = 0 V or Y = 0 V), multiplier cell in the feedback path around an integrating buffer. where 0 V is expected on the output (W = 0 V). For example, The inputs to this feedback multiplier are the difference of the when the ADL5391 is used as a VGA and a large amount of output signal and the summing input, W − Z, and the internal attenuation is needed, the maximum attenuation is determined scaling reference, U. At dc, the integrating buffer ensures that by the input dc offset. the output of both multipliers is exactly 0, therefore Applying the proper voltage on the Z input removes the W offset. (W − Z)xU = XY, or W = XY/U + Z (2) Calibration can be accomplished by making the appropriate cross plots and adjusting the Z input to remove the offset. By using a feedback multiplier that is identical to the main multiplier, the scaling is traced back solely to U, which is Additionally, gain scaling can be adjusted by applying a dc voltage an accurate reference generated on-chip. As is apparent in to the GADJ pin, as shown in Figure 5. Equation 2, noise, drift, or distortion that is common to both
BASIC CONNECTIONS
multipliers is rejected to first-order because the feedback multiplier essentially compensates the impairments generated
Multiplier Connections
in the main multiplier. The best ADL5391 performance is achieved when the X, Y, and Z inputs and W output are driven differentially; however, they The scaling factor, U, is fixed by design to 1.12 V. However, the can be driven single-ended. Single-ended-to-differential multiplier gain, α, can be adjusted by driving the GADJ pin with transformations (or differential-to-single-ended transformations) a voltage ranging from 0 V to 2 V. If left floating, then α = 1 or can be done using a balun or active components, such as the 0 dB, and the overall scaling is simply U = 1 V. For VGADJ = 0 V, AD8313, the AD8132 (both with operation down to dc), or the the gain is lowered by approximately 4 dB; for VGADJ = 2 V, the AD8352 (for higher drive capability). If using the ADL5391 gain is raised by approximately 6 dB. Figure 5 shows the single-ended without ac coupling capacitors, the reference relationship between α(V/V) and VGADJ. voltage of 2.5 V needs to be taken into account. Voltages above 2.5 V are positive voltages and voltages below 2.5 V are negative voltages. Care needs to be taken not to load the ADL5391 too heavily, the maximum reference current available is 50 mA. Rev. A | Page 10 of 15 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Theory Calibration Basic Connections Multiplier Connections Matching the Input/Output Wideband Voltage-Controlled Amplifier/Amplitude Modulator Squaring and Frequency Doubling Use as a Detector Evaluation Board Outline Dimensions Ordering Guide