Datasheet MTP2N50E (Motorola)
| 制造商 | Motorola |
| 描述 | TMOS E-FET Power Field Effect Transistor - N-Channel Enhancement-Mode Silicon Gate |
| 页数 / 页 | 8 / 1 — Order this document. SEMICONDUCTOR TECHNICAL DATA. by MTP2N50E/D. … |
| 文件格式/大小 | PDF / 253 Kb |
| 文件语言 | 英语 |
Order this document. SEMICONDUCTOR TECHNICAL DATA. by MTP2N50E/D. Motorola Preferred Device
该数据表的模型线
文件文字版本
Order this document SEMICONDUCTOR TECHNICAL DATA by MTP2N50E/D
Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET
This high voltage MOSFET uses an advanced termination
2.0 AMPERES
scheme to provide enhanced voltage–blocking capability without
500 VOLTS
degrading performance over time. In addition, this advanced TMOS
RDS(on) = 3.6 OHM
E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete D Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature G
CASE 221A–06, Style 5 TO–220AB
S
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage VDSS 500 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate–Source Voltage — Continuous VGS ± 20 Vdc — Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk Drain Current — Continuous ID 2.0 Adc — Continuous @ 100°C ID 1.6 — Single Pulse (tp ≤ 10 µs) IDM 6.0 Apk Total Power Dissipation PD 75 Watts Derate above 25°C 0.6 W/°C Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 61 mJ (VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.5 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance — Junction to Case RθJC 1.67 °C/W — Junction to Ambient RθJA 62.5 Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola TMOS Power MOSFET T Motorola, Inc. 1995 ransistor Device Data 1
Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate TMOS POWER FET
This high voltage MOSFET uses an advanced termination
2.0 AMPERES
scheme to provide enhanced voltage–blocking capability without
500 VOLTS
degrading performance over time. In addition, this advanced TMOS
RDS(on) = 3.6 OHM
E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete D Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature G
CASE 221A–06, Style 5 TO–220AB
S
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage VDSS 500 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate–Source Voltage — Continuous VGS ± 20 Vdc — Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk Drain Current — Continuous ID 2.0 Adc — Continuous @ 100°C ID 1.6 — Single Pulse (tp ≤ 10 µs) IDM 6.0 Apk Total Power Dissipation PD 75 Watts Derate above 25°C 0.6 W/°C Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 61 mJ (VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.5 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance — Junction to Case RθJC 1.67 °C/W — Junction to Ambient RθJA 62.5 Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola TMOS Power MOSFET T Motorola, Inc. 1995 ransistor Device Data 1