Datasheet HMC903LP3E (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | GaAs, pHEMT, MMIC, Low Noise Amplifier, 6 GHz to 17 GHz |
| 页数 / 页 | 13 / 5 — Data Sheet. HMC903LP3E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. DD1. … |
| 修订版 | I |
| 文件格式/大小 | PDF / 312 Kb |
| 文件语言 | 英语 |
Data Sheet. HMC903LP3E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. DD1. DD2. NIC. GND. TOP VIEW. (Not to Scale). RFIN. RFOUT. PACKAGE. BASE
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Data Sheet HMC903LP3E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C DD1 DD2 C NI V V NI 16 15 14 13 NIC 1 12 NIC GND 2 HMC903LP3E 11 GND TOP VIEW (Not to Scale) RFIN 3 10 RFOUT NIC 4 9 NIC 5 6 7 8 PACKAGE C C BASE NI GG1 GG2 NI V V GND NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. EXPOSED PAD. THE PACKAGE BOTTOM HAS
002
AN EXPOSED METAL GROUND PADDLE THAT MUST CONNECT TO RF/DC GROUND.
14479- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 5, 8, 9, NIC Not Internally Connected. However, all data shown was measured with these pins connected to RF/dc ground 12, 13, 16 externally. 2, 11 GND Ground. Connect these pins to RF/dc ground. See Figure 3 for the interface schematic. 3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. 6, 7 V , V Optional Gate Controls for the Amplifier. If left open, the amplifier runs self biased at the standard current. GG1 GG2 Applying a negative voltage reduces the drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. 10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 14, 15 V , V Power Supply Voltages for the Amplifier. See assembly for the required external components (see Figure 23 DD1 DD2 and Figure 24). See Figure 7 for the interface schematic. EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must connect to RF/dc ground.
INTERFACE SCHEMATICS GND RFOUT
003 006 14479- 14479- Figure 3. GND Interface Schematic Figure 6. RFOUT Interface Schematic
RFIN VDD1,
004
VDD2
007 14479- 14479- Figure 4. RFIN Interface Schematic Figure 7. VDD1 and VDD2 Interface Schematic 005
VGG1, VGG2
14479- Figure 5. VGG1 and VGG2 Interface Schematic Rev. I | Page 5 of 13 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications 6 GHz to 16 GHz Frequency Range 16 GHz to 17 GHz Frequency Range Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power Up Recommended Bias Sequence During Power Down Evaluation PCB Typical Application Circuits Outline Dimensions Ordering Guide
Data Sheet HMC903LP3E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C DD1 DD2 C NI V V NI 16 15 14 13 NIC 1 12 NIC GND 2 HMC903LP3E 11 GND TOP VIEW (Not to Scale) RFIN 3 10 RFOUT NIC 4 9 NIC 5 6 7 8 PACKAGE C C BASE NI GG1 GG2 NI V V GND NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. EXPOSED PAD. THE PACKAGE BOTTOM HAS
002
AN EXPOSED METAL GROUND PADDLE THAT MUST CONNECT TO RF/DC GROUND.
14479- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 5, 8, 9, NIC Not Internally Connected. However, all data shown was measured with these pins connected to RF/dc ground 12, 13, 16 externally. 2, 11 GND Ground. Connect these pins to RF/dc ground. See Figure 3 for the interface schematic. 3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. 6, 7 V , V Optional Gate Controls for the Amplifier. If left open, the amplifier runs self biased at the standard current. GG1 GG2 Applying a negative voltage reduces the drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. 10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 14, 15 V , V Power Supply Voltages for the Amplifier. See assembly for the required external components (see Figure 23 DD1 DD2 and Figure 24). See Figure 7 for the interface schematic. EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must connect to RF/dc ground.
INTERFACE SCHEMATICS GND RFOUT
003 006 14479- 14479- Figure 3. GND Interface Schematic Figure 6. RFOUT Interface Schematic
RFIN VDD1,
004
VDD2
007 14479- 14479- Figure 4. RFIN Interface Schematic Figure 7. VDD1 and VDD2 Interface Schematic 005
VGG1, VGG2
14479- Figure 5. VGG1 and VGG2 Interface Schematic Rev. I | Page 5 of 13 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications 6 GHz to 16 GHz Frequency Range 16 GHz to 17 GHz Frequency Range Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power Up Recommended Bias Sequence During Power Down Evaluation PCB Typical Application Circuits Outline Dimensions Ordering Guide