link to page 13 link to page 13 ADRF5547Data SheetParameterTest Conditions/CommentsMinTypMaxUnit DIGITAL INPUTS SWCTRL-ChAB, PD-ChAB Low (VIL) 0 0.7 V High (VIH)2 1.4 VDD V BP-ChA, BP-ChB Low (VIL) 0 0.3 V High (VIH)2 1.0 VDD V SUPPLY CURRENT (IDD) VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB = 5 V per channel High Gain Mode 86 mA Low Gain Mode 36 mA Power-Down Mode 12 mA Transmit Current (Switch) SWVDD-ChAB = 5 V 4.3 mA DIGITAL INPUT CURRENTS SWCTRL-ChAB, PD-ChAB, BP-ChA, BP-ChB = 5 V per channel SWCTRL-ChAB 0.0004 mA PD-ChAB 0.2 mA BP-ChA, BP-ChB 0.4 mA 1 See Table 5 and Table 6. 2 VDD (shown in the maximum column) is the voltage of the SWVDD-ChAB, VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB pins. 3 Measured at the exposed pad (EPAD). Rev. A | Page 4 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE