Datasheet ADA4320-1 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver |
| 页数 / 页 | 16 / 4 — Parameter. Conditions. Min Typ. Max. Unit. LOGIC INPUTS … |
| 修订版 | A |
| 文件格式/大小 | PDF / 365 Kb |
| 文件语言 | 英语 |
Parameter. Conditions. Min Typ. Max. Unit. LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC). Table 2. Parameter. Min. Typ
该数据表的模型线
文件文字版本
ADA4320-1
Parameter Conditions Min Typ Max Unit
POWER CONTROL Transmit Enable Settling Time TXEN = 0 to 1, Gain Code 60, no input signal 5.5 μs Transmit Disable Settling Time TXEN = 1 to 0, Gain Code 60, no input signal 7 μs Output Switching Transients Gain Code 60 20 mV p-p Gain Code 01 2 mV p-p POWER SUPPLY Operating Range 4.75 5.00 5.25 V Quiescent Current At Maximum Gain Gain Code 60, Current Level 3 260 300 mA Gain Code 60, Current Level 2 235 270 mA Gain Code 60, Current Level 1 210 250 mA Gain Code 60, Current Level 0 180 210 mA At Minimum Gain Gain Code 01, Current Level 3 77 100 mA Gain Code 01, Current Level 2 73 95 mA Gain Code 01, Current Level 1 70 90 mA Gain Code 01, Current Level 0 65 80 mA TXEN = 0, all gain codes, all current levels 12 15 mA SLEEP = 0 (power-down) 12 80 μA OPERATING TEMPERATURE RANGE −40 +85 °C
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VS = 5 V; full temperature range.
Table 2. Parameter Min Typ Max Unit
Logic 1 Voltage 2.0 VS V Logic 0 Voltage 0 0.8 V Digital Input Leakage Current (Both Logic Levels, All Digital Pins) −5 +5 μA Rev. A | Page 4 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
Parameter Conditions Min Typ Max Unit
POWER CONTROL Transmit Enable Settling Time TXEN = 0 to 1, Gain Code 60, no input signal 5.5 μs Transmit Disable Settling Time TXEN = 1 to 0, Gain Code 60, no input signal 7 μs Output Switching Transients Gain Code 60 20 mV p-p Gain Code 01 2 mV p-p POWER SUPPLY Operating Range 4.75 5.00 5.25 V Quiescent Current At Maximum Gain Gain Code 60, Current Level 3 260 300 mA Gain Code 60, Current Level 2 235 270 mA Gain Code 60, Current Level 1 210 250 mA Gain Code 60, Current Level 0 180 210 mA At Minimum Gain Gain Code 01, Current Level 3 77 100 mA Gain Code 01, Current Level 2 73 95 mA Gain Code 01, Current Level 1 70 90 mA Gain Code 01, Current Level 0 65 80 mA TXEN = 0, all gain codes, all current levels 12 15 mA SLEEP = 0 (power-down) 12 80 μA OPERATING TEMPERATURE RANGE −40 +85 °C
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VS = 5 V; full temperature range.
Table 2. Parameter Min Typ Max Unit
Logic 1 Voltage 2.0 VS V Logic 0 Voltage 0 0.8 V Digital Input Leakage Current (Both Logic Levels, All Digital Pins) −5 +5 μA Rev. A | Page 4 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE