Datasheet ADA4320-1 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver |
| 页数 / 页 | 16 / 6 — MAXIMUM POWER DISSIPATION. Table 4. Parameter Rating. THERMAL RESISTANCE. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 365 Kb |
| 文件语言 | 英语 |
MAXIMUM POWER DISSIPATION. Table 4. Parameter Rating. THERMAL RESISTANCE. ESD CAUTION. Table 5. Thermal Resistance Package Type
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ADA4320-1 ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION Table 4. Parameter Rating
The maximum safe power dissipation in the ADA4320-1 package Supply Voltage 5.5 V is limited by the associated rise in junction temperature (TJ) on Maximum Power Dissipation 1.65 W the die. At approximately 150°C, which is the glass transition Storage Temperature Range −65°C to +125°C temperature, the plastic changes its properties. Even temporarily Operating Temperature Range −40°C to +85°C exceeding this temperature limit can change the stresses that Lead Temperature (Soldering, 10 sec) 300°C the package exerts on the die, permanently shifting the parametric Junction Temperature 150°C performance of the ADA4320-1. Exceeding a junction temperature of 150°C for an extended time can result in changes in the silicon Stresses above those listed under Absolute Maximum Ratings devices, potentially causing failure. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Airflow increases heat dissipation, effectively reducing θJA. In other conditions above those indicated in the operational addition, more metal directly in contact with the package leads section of this specification is not implied. Exposure to absolute from metal traces, through-holes, ground, and power planes, maximum rating conditions for extended periods may affect reduces the θJA. The exposed paddle on the underside of the device reliability. package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified θJA.
THERMAL RESISTANCE
θJA is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in
ESD CAUTION
EIA/JESD 51-7.
Table 5. Thermal Resistance Package Type θJA θJC Unit
24-lead LFCSP 31.2 5.7 °C/W Rev. A | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
MAXIMUM POWER DISSIPATION Table 4. Parameter Rating
The maximum safe power dissipation in the ADA4320-1 package Supply Voltage 5.5 V is limited by the associated rise in junction temperature (TJ) on Maximum Power Dissipation 1.65 W the die. At approximately 150°C, which is the glass transition Storage Temperature Range −65°C to +125°C temperature, the plastic changes its properties. Even temporarily Operating Temperature Range −40°C to +85°C exceeding this temperature limit can change the stresses that Lead Temperature (Soldering, 10 sec) 300°C the package exerts on the die, permanently shifting the parametric Junction Temperature 150°C performance of the ADA4320-1. Exceeding a junction temperature of 150°C for an extended time can result in changes in the silicon Stresses above those listed under Absolute Maximum Ratings devices, potentially causing failure. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Airflow increases heat dissipation, effectively reducing θJA. In other conditions above those indicated in the operational addition, more metal directly in contact with the package leads section of this specification is not implied. Exposure to absolute from metal traces, through-holes, ground, and power planes, maximum rating conditions for extended periods may affect reduces the θJA. The exposed paddle on the underside of the device reliability. package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified θJA.
THERMAL RESISTANCE
θJA is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in
ESD CAUTION
EIA/JESD 51-7.
Table 5. Thermal Resistance Package Type θJA θJC Unit
24-lead LFCSP 31.2 5.7 °C/W Rev. A | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE