Datasheet AD8324 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 3.3 V DOCSIS 2.0 Upstream Cable Line Driver |
| 页数 / 页 | 16 / 4 — AD8324. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 427 Kb |
| 文件语言 | 英语 |
AD8324. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit. LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
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AD8324 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Operating Range 3.13 3.3 3.47 V Quiescent Current Maximum gain 195 207 235 mA Minimum gain 25 39 50 mA Transmit disable (TXEN = 0) 1 2.5 4 mA SLEEP mode (power down) 30 500 µA OPERATING TEMPERATURE RANGE 20-lead LFCSP −40 +85 °C 20-lead QSOP −25 +70 °C 1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB at 10 MHz. 2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C. 3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 4 Measured through a 1:1 transformer. 5 Specification is worst case over all gain codes. 6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit
Logic 1 Voltage 2.1 3.3 V Logic 0 Voltage 0 0.8 V Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN 0 20 nA Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN −600 −100 nA Logic 1 Current (VINH = 3.3 V), TXEN 50 190 µA Logic 0 Current (VINL = 0 V), TXEN −250 −30 µA Logic 1 Current (VINH = 3.3 V), SLEEP 50 190 µA Logic 0 Current (VINL = 0 V), SLEEP −250 −30 µA Rev. C | Page 4 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE
POWER SUPPLY Operating Range 3.13 3.3 3.47 V Quiescent Current Maximum gain 195 207 235 mA Minimum gain 25 39 50 mA Transmit disable (TXEN = 0) 1 2.5 4 mA SLEEP mode (power down) 30 500 µA OPERATING TEMPERATURE RANGE 20-lead LFCSP −40 +85 °C 20-lead QSOP −25 +70 °C 1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB at 10 MHz. 2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C. 3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 4 Measured through a 1:1 transformer. 5 Specification is worst case over all gain codes. 6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit
Logic 1 Voltage 2.1 3.3 V Logic 0 Voltage 0 0.8 V Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN 0 20 nA Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN −600 −100 nA Logic 1 Current (VINH = 3.3 V), TXEN 50 190 µA Logic 0 Current (VINL = 0 V), TXEN −250 −30 µA Logic 1 Current (VINH = 3.3 V), SLEEP 50 190 µA Logic 0 Current (VINL = 0 V), SLEEP −250 −30 µA Rev. C | Page 4 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE