AD8324Data Sheet180110Hz)f = 10MHz/)160100TXEN = 1-p(nVp90EV140m ( S80NOIS 120NT IE70100LTAGE60ORANS T8050D VTDOCSIS 2.0 BETWEEN BURSTRSTRANSIENT SPECIFICATIONRRE4060FEN BU E3040EAD8324UT REW20T20BE10 -021 0 OUTP 39- 0 04339-0-019 0 043 0612182430364248546006121824303642485460GAIN CONTROL (Decimal Code)GAIN CONTROL (Decimal Code) Figure 19. Output Referred Voltage Noise vs. Gain Control Figure 21. Between Burst Transient vs. Gain Control 210190TA = 25°C170NT (mA)150CURRE 130 LY P P 110U T S N90E C S70QUIE5030 04339-0-020 06121824303642485460GAIN CONTROL (Decimal Code) Figure 20. Quiescent Supply Current vs. Gain Control Rev. C | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE